Xilinx RocketIO User Manual

Also see for RocketIO: User guide User guide User guide

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Xilinx RocketIO User Manual Manual pdf 146 page image

146 www.xilinx.com RocketIO™ Transceiver User GuideUG024 (v3.0) February 22, 2007Appendix C: Related Online DocumentsRa backplane bus. Utilization of a hardware test-and-set lock mechanism, along with asoftware protocol to test for a semaphore grant prior to accessing the shared memory,guarantees atomic access to the shared memory.XAPP649: SONET Rate Conversion in Virtex-II Pro DevicesThe RocketIO transceivers have several modes of operation, but all modes rely on theinternal transmitter clock being multiplied by 20 for data transmission. For example, a20-bit data stream passed to the unit at 125 MHz is serialized and retransmitted at2.5 Gb/s. At a 156.25 MHz input, the output is at its maximum speed of 3.125 Gb/s. Theparallel data stream applied to the RocketIO transceiver can either be 20 bits direct, or itcan be written as 16 bits, to which 8b/10b coding is applied to generate the 20 bits required.However, there is a class of applications, typically in SONET processing systems, wherethe data path is 16 bits wide, running at 155.52 MHz. The designer would ideally apply thedata directly to the RocketIO transceiver for onward transmission at 155.52 x 16 =2.48832 Gb/s. Since this cannot be done in Virtex-II Pro devices, this application notedescribes the logic necessary to perform this function.This application note is divided into two sections, the first is the logic necessary for thedata width conversion, and the second describes the clocking characteristics required bythe RocketIO transceiver.XAPP651: SONET and OTN Scramblers/DescramblersBoth SONET and OTN are standards for data transmission over fibre optic links. Thisimplies a need for clock recovery at the receiver, which in turn requires a guaranteedminimum number of transitions in the incoming serial data stream. The mechanism toachieve this transition density, similar for both SONET and OTN, is known as scrambling.The scrambling (and descrambling) function is independent of the serial data rate used.Serial data for transmission is added to the output of a pseudo-random number generator,running at the same clock frequency. The same circuit is used in the receiver to recover theoriginal data transmitted. Obviously, the pseudo-random number generators at each endof the link must be in phase. This is achieved using a known pattern of framinginformation (which is actually transmitted unscrambled). This is covered in more detail inXAPP652.XAPP652: Word Alignment and SONET/SDH DeframingThis application note describes the logic to perform basic word alignment and deframingspecifically for SONET/SDH systems, where data is being processed at 16 bits or 64 bitsper clock cycle.XAPP660: Partial Reconfiguration of RocketIO Pre-emphasisand Differential Swing Control AttributesThis application note describes a pre-engineered solution for Virtex-II Pro devices usingthe IBM PowerPC™ 405 core to perform a partial reconfiguration of the RocketIO™ multi-gigabit transceivers (MGTs) pre-emphasis and differential swing control attributes. Thissolution is ideal for applications where these attributes must be modified to optimize theMGT signal transmission for various system environments while leaving the rest of theFPGA design unchanged. The hardware and software elements of this solution can beeasily integrated into any Virtex-II Pro design. The associated reference design supportsthe following devices: XC2VP4, XC2VP7, XC2VP20, and XC2VP50. The design discussedProduct Not Recommended for New Designs