Xilinx RocketIO User Manual
Also see for RocketIO: User guideUser guideUser guide
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RocketIO™ Transceiver User Guide www.xilinx.com 75UG024 (v3.0) February 22, 2007Clock Recovery RCLK_COR_SEQ_LENTo define the CCS length, this attribute takes the integer value 1, 2, 3, or 4. Table 2-16 showswhich sequences are used for the four possible settings of CLK_COR_SEQ_LEN.CLK_COR_INSERT_IDLE_FLAG,CLK_COR_KEEP_IDLE,CLK_COR_REPEAT_WAITThese attributes help control how clock correction is implemented.CLK_COR_INSERT_IDLE_FLAG is a TRUE/FALSE attribute that defines the output ofthe RXRUNDISP port. When set to TRUE, RXRUNDISP is raised for the first byte of eachinserted (repeated) clock correction sequence (8B/10B decoding enabled). When set toFALSE (default), RXRUNDISP denotes the running disparity of RXDATA (8B/10Bdecoding enabled).CLK_COR_KEEP_IDLE is a TRUE/FALSE attribute that controls whether or not the finalbyte stream must retain at least one clock correction sequence. When set to FALSE(default), the clock correction logic is allowed to remove all clock correction sequences ifneeded to recenter the elastic buffer. When set to TRUE, it forces the clock correction logicto retain at least one clock correction sequence per continuous stream of clock correctionsequences.Example: Elastic buffer is 75% full and clock correction is needed. (IDLE is the defined clockcorrection sequence.)Data stream written into elastic buffer:Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = FALSE)Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = TRUE)CLK_COR_REPEAT_WAIT is an integer attribute (0-31) that controls frequency ofrepetition of clock correction operations. This attribute specifies the minimum number ofRXUSRCLK cycles without clock correction that must occur between successive clockcorrections. For example, if this attribute is 3, then at least three RXUSRCLK cycles withoutTable 2-16: Applicable Clock Correction SequencesCLK_COR_SEQ_LEN CLK_COR_SEQ_1That Are ApplicableCLK_COR_SEQ_2That Are Applicable(1)1 1_1 2_12 1_1, 1_2 2_1, 2_23 1_1, 1_2, 1_3 2_1, 2_2, 2_34 1_1, 1_2, 1_3. 1_4 2_1, 2_2, 2_3, 2_4Notes:1. Applicable only if CLK_COR_SEQ_2_USE is set to TRUE.D0 IDLE IDLE IDLE IDLE D1 D2D0 D1 D2D0 IDLE D1 D2Product Not Recommended for New Designs |
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