Xilinx SP605 Hardware User's Manual

Also see for SP605: Hardware Tutorial User guide Hardware setup guide

Contents

SP605 Hardware User Guide www.xilinx.com 19UG526 (v1.9) February 14, 2019Detailed DescriptionSee the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 15]Also, see the Spartan-6 FPGA Memory Controller User Guide (UG388). [Ref 3]3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACTconfiguration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flashthrough a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing anexternal SPI flash memory device.The SP605 SPI interface has two parallel connected configuration options (Figure 1-3): anSPI X4 (Winbond W25Q64FVSFIG) 64-Mb flash memory device (U32) and a flashprogramming header (J17). J17 supports a user-defined SPI mezzanine board. The SPIconfiguration source is selected via SPI select jumper J46. For details on configuring theFPGA, see Configuration Options.X-Ref Target - Figure 1-3Figure 1-3: J17 SPI Flash Programming HeaderSPI ProgFPGA_D1_MISO2J17123456789FPGA_D2_MISO3FPGA_PROG_BFPGA_MOSI_CSI_B_MISO0SPI_CS_BFPGA_CCLKFPGA_D0_DIN_MISO_MISO1UG526_03_092409GNDVCC3V3SilkscreenTMSTDITDOTCKGND3V3HDR_1X9