SP605 Hardware User Guide www.xilinx.com 65UG526 (v1.9) February 14, 2019Appendix CXilinx Design ConstraintsOverviewThe Xilinx Design Constraints (XDC) file template provides for designs targeting the SP605evaluation board. Net names in the constraints correlate with net names on the latest SP605evaluation board schematic. Identify the appropriate pins and replace the net names withnet names in the user RTL.See the Constraints Guide (UG625) [Ref 12] for more information.Note: The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V(nonadjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces arecompatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.Note: The latest version of the Xilinx constraint file can be found on the Spartan-6 FPGA SP605Evaluation Kit website.
