Xilinx SP605 Hardware User's Manual

Also see for SP605: Hardware Tutorial User guide Hardware setup guide

Contents

60 www.xilinx.com SP605 Hardware User GuideUG526 (v1.9) February 14, 2019Chapter 1: SP605 Evaluation BoardConfiguration OptionsThe FPGA on the SP605 Evaluation Board can be configured by the following methods:• 3. SPI x4 Flash• 4. Linear BPI Flash• 5. System ACE CF and CompactFlash Connector• 6. USB JTAGFor more information, refer to the Spartan-6 FPGA Configuration User Guide (UG380).[Ref 2]With the mode switch SW1 set to 01, the SP605 will attempt to boot or load a bitstreamfrom either the SPI X4 Flash device U32 or a user supplied SPI Flash memory mezzaninecard installed on the SPI programming header J17, depending on the SPI select jumper J46configuration, as shown in Table 1-32. With the mode set to 00, the SP605 will attempt toboot or load a bitstream from Linear Flash device U25 (BPI).With the mode switch SW1 set to 10, if a CompactFlash (CF) card is installed in the CFsocket U37, System ACE CF will attempt to load a bitstream from the CF card imageaddress pointed to by the image select switch S1. With no CF card present, the SP605 can beconfigured via the onboard JTAG controller and USB download cable as described in 6.USB JTAG.Table 1-32: SP605 FPGA Configuration ModesConfigurationMode M[1:0] Bus Width CCLKDirection Configuration Solution User Guide SectionMaster Serial/SPI 01 1, 2, 4 (1) Output SPI X4 Memory U32 (J46 on), orExternal SPI Header J17 (J46 off) 3. SPI x4 FlashMasterSelectMAP/BPI (2) 00 8, 16 Output Linear Flash Memory U25 (BPI) 4. Linear BPI FlashJTAG(3) xx 1 Input(TCK)Xilinx Platform Cable USBplugged into J4 6. USB JTAGSlave SelectMAP (2) 10 8, 16 Input System ACE CF Controller andCompactFlash Card5. System ACE CF andCompactFlash ConnectorSlave Serial (4) 11 1 Input Not Supported –Notes:1. Utilizing dual and quad SPI modes.2. Parallel configuration mode bus is auto-detected by the configuration logic.3. Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of themode pin settings.4. Default setting due to internal pull-up termination on Mode pins.