Xilinx SP605 Hardware User's Manual

Also see for SP605: Hardware Tutorial User guide Hardware setup guide

Contents

SP605 Hardware User Guide www.xilinx.com 25UG526 (v1.9) February 14, 2019Detailed DescriptionSee the System ACE CF product page, System ACE file generation information, and theSystem ACE CompactFlash Solution Data Sheet (DS080) [Ref 5] for more information.6. USB JTAGJTAG configuration is provided through onboard USB-to-JTAG configuration logic wherea computer host accesses the SP605 JTAG chain through a Type-A (computer host side) toType-Mini-B (SP605 side) USB cable. The JTAG chain of the board is illustrated inFigure 1-6. JTAG configuration is allowable at any time under any mode pin setting. JTAGinitiated configuration takes priority over the mode pin settings.FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAGaccess to the FPGA on the basic SP605 board (without FMC expansion modules installed),AA1 SYSACE_MPBRDY 39 MPBRDYW4 SYSACE_MPCE 42 MPCEAA2 SYSACE_MPIRQ 41 MPIRQT6 SYSACE_MPOE 77 MPOET5 SYSACE_MPWE 76 MPWEG17 SYSACE_CFGTDI 81 CFGTDIA21 FPGA_TCK 80 CFGTCKE18 FPGA_TDI 82 CFGTDOD20 FPGA_TMS 85 CFGTMSN19 CLK_33MHZ_SYSACE(2) 93 CLKNotes:1. U17 System ACE CF controller 3.3V signals as named are wired to a set of TXB0108 3.3V-to-1.5V levelshifters. The nets between the 1.5V side of the level shifters and the U1 FPGA have the same nameswith _LS appended.2. The System ACE CF clock is sourced from U29 32.000MHz oscillator.Table 1-8: System ACE CF Connections (Cont’d)U1 FPGA Pin Schematic Net Name (1) U17 XCCACETQ144IPin Number Pin NameX-Ref Target - Figure 1-6Figure 1-6: JTAG Chain DiagramFMC LPCTDOU1FPGATDITSTTDI CFGTDOCFGTDITSTTDO TDOSystem ACE CF3.3V 2.5VTDIBufferUSB HeaderJ4J2J19U17UG526_06_092409