Xilinx SP605 Hardware User's Manual

Also see for SP605: Hardware Tutorial User guide Hardware setup guide

Contents

SP605 Hardware User Guide www.xilinx.com 47UG526 (v1.9) February 14, 2019Detailed DescriptionUser SIP HeaderThe SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access.Four pins of J55 are wired to the FPGA through 200Ω series resistors and a level shifter, andthe remaining two J55 pins are wired to 3.3V and GND. The J55 header is described inFigure 1-18 and Table 1-26.X-Ref Target - Figure 1-18Figure 1-18: User SIP Header J55VCC3V3HDR_1x6GPIO_HEADER_3GPIO_HEADER_2GPIO_HEADER_1GPIO_HEADER_0215%1/16W200R28112R2802001/16W5%123456J55DNP12R2822001/16W5%215%1/16W200R283TXB0108VCCBB1B2B3B4B6B7GNDA3A8OEA4A5A7A6B5A1A2B8VCCAVCC1V5_FPGA VCC3V3GPIO_HEADER_0GPIO_HEADER_1GPIO_HEADER_2GPIO_HEADER_3GPIO_HEADER_0_LSGPIO_HEADER_1_LSNCNCNCNC2123115786510941113141617182019U5212X5R10V0.1UFC38521 C3840.1UF10VX5RNCNCNCNCGPIO_HEADER_2_LSGPIO_HEADER_3_LSU1 FPGA PinG7H6D1R7UG526_18 _092409Table 1-26: User SIP Header ConnectionsU1 FPGA Pin Schematic Net Name GPIO Header PinG7 GPIO_HEADER_0 J55.1H6 GPIO_HEADER_1 J55.2D1 GPIO_HEADER_2 J55.3R7 GPIO_HEADER_3 J55.4– GND J55.5– VCC3V3 J55.6Notes:1. Each GPIO_HEADER_n signal is sourced from the FPGA as<netname>_LS to a level shifter, then to the J55 header.2. Each GPIO_HEADER_n net has a 200Ω series resistor between thelevel shifter and its respective header pin.