104 www.xilinx.com Spartan-3E Starter Kit Board User GuideUG230 (v1.0) March 9, 2006Chapter 13: DDR SDRAM RThe differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have bestaccess to one of the FPGA’s Digital Clock Managers (DCMs). This path is required whenusing the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controllerIP core documentation is also available from within the EDK 8.1i development software(see “Related Resources,” page 107).DDR SDRAM ConnectionsTable 13-1 shows the connections between the FPGA and the DDR SDRAM.Table 13-1: FPGA-to-DDR SDRAM ConnectionsCategoryDDR SDRAMSignal NameFPGA PinNumber FunctionAddressSD_A12 P2 Address inputsSD_A11 N5SD_A10 T2SD_A9 N4SD_A8 H2SD_A7 H1SD_A6 H3SD_A5 H4SD_A4 F4SD_A3 P1SD_A2 R2SD_A1 R3SD_A0 T1
