Xilinx Spartan-3E User Manual

Also see for Spartan-3E: Quick start guide

Contents

62 www.xilinx.com Spartan-3E Starter Kit Board User GuideUG230 (v1.0) March 9, 2006Chapter 8: PS/2 Mouse/Keyboard Port Rorganized differently for a mouse and keyboard. Furthermore, the keyboard interfaceallows bidirectional data transfers so the host device can illuminate state LEDs on thekeyboard.The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals areonly driven when data transfers occur; otherwise they are held in the idle state at logicHigh. The timing defines signal requirements for mouse-to-host communications andbidirectional keyboard communications. As shown in Figure 8-2, the attached keyboard ormouse writes a bit on the data line when the clock signal is High, and the host reads thedata line when the clock signal is Low.KeyboardThe keyboard uses open-collector drivers so that either the keyboard or the host can drivethe two-wire bus. If the host never sends data to the keyboard, then the host can use simpleinput pins.A PS/2-style keyboard uses scan codes to communicate key press data. Nearly allkeyboards in use today are PS/2 style. Each key has a single, unique scan code that is sentwhenever the corresponding key is pressed. The scan codes for most keys appear inFigure 8-3.If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms orso. When a key is released, the keyboard sends an “F0” key-up code, followed by the scancode of the released key. The keyboard sends the same scan code, regardless if a key hasdifferent shift and non-shift characters and regardless whether the Shift key is pressed ornot. The host determines which character is intended.Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore,they might send more than one scan code. When an extended key is released, an “E0 F0”key-up code is sent, followed by the scan code.Table 8-2: PS/2 Bus TimingSymbol Parameter Min MaxT CK Clock High or Low Time 30 μs 50 μsT SU Data-to-clock Setup Time 5 μs 25 μsT HLD Clock-to-data Hold Time 5 μs 25 μsFigure 8-2: PS/2 Bus Timing WaveformsTCKTSUTHLDTCKEdge 0 Edge 10CLK (PS2C)DATA (PS2D)'0' start bit '1' stop bitUG230_c8_02_021806