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Xilinx Spartan-3E User Manual
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Xilinx Spartan-3E User Manual
Also see for Spartan-3E:
Quick start guide
Table of content
Contents
revision history
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Acknowledgements
Additional Resources
Choose the Starter Kit Board for Your Needs
Key Components and Features
Design Trade-Offs
Slide Switches
Push-Button Switches
UCF Location Constraints
Rotary Shaft Encoder
Operation
Overview
Clock Connections
Clock Period Constraints
Configuration Mode Jumpers
PROG Push Button
Programming the FPGA, CPLD, or Platform Flash PROM via USB
Programming via iMPACT
Programming Platform Flash PROM via USB
Generating the PROM File
Programming the Platform Flash PROM
Character LCD Interface Signals
Command Set
Disabled
Display On/Off
Function Set
Transferring 8-Bit Data over the 4-Bit Interface
Writing Data to the Display
Signal Timing for a 60 Hz, 640x480 VGA Display
VGA Signal Timing
Keyboard
Mouse
Voltage Supply
SPI Communication
Interface Signals
SPI Communication Details
Specifying the DAC Output Voltage
Digital Outputs from Analog Inputs
Programmable Pre-Amplifier
SPI Control Interface
Disable Other Devices on the SPI Bus to Avoid Contention
StrataFlash Connections
Shared Connections
Control
Configuring from SPI Flash
Creating an SPI Serial Flash PROM File
Formatting an SPI Flash PROM File
Downloading the Design to SPI Flash
Insert Jumper on JP8 and Hold PROG_B Low
Programming the SPI Flash with the XSPI Software
Additional Design Details
Other SPI Flash Control Signals
Related Resources
ddr sdram
DDR SDRAM Connections
Ethernet PHY Connections
MicroBlaze Ethernet IP Cores
Hirose 100-pin FX2 Edge Connector (J3)
Voltage Supplies to the Connector
Compatible Board
Using Differential Inputs
Using Differential Outputs
Six-Pin Accessory Headers
Header J4
Connectorless Debugging Port Landing Pads (J6)
Chapter 16: XC2C64A CoolRunner-II CPLD
FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header
RS-232 Ports, VGA Port, and PS/2 Port
Ethernet PHY, Magnetics, and RJ-11 Connector
Voltage Regulators
FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections
FPGA I/O Banks 0 and 1, Oscillators
Power Supply Decoupling
XC2C64A CoolRunner-II CPLD
Spartan-3E Start Kit Board User Guide
www.xilinx.com
145
UG230 (v1.0) March 9, 2006
FPGA I/O Banks 2 and 3
R
Figure A-7:
Schematic Sheet 8
UG2
3
0_A
a
_07_021806
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