Contents - revision history
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Acknowledgements
- Additional Resources
- Choose the Starter Kit Board for Your Needs
- Key Components and Features
- Design Trade-Offs
- Slide Switches
- Push-Button Switches
- UCF Location Constraints
- Rotary Shaft Encoder
- Operation
- Overview
- Clock Connections
- Clock Period Constraints
- Configuration Mode Jumpers
- PROG Push Button
- Programming the FPGA, CPLD, or Platform Flash PROM via USB
- Programming via iMPACT
- Programming Platform Flash PROM via USB
- Generating the PROM File
- Programming the Platform Flash PROM
- Character LCD Interface Signals
- Command Set
- Disabled
- Display On/Off
- Function Set
- Transferring 8-Bit Data over the 4-Bit Interface
- Writing Data to the Display
- Signal Timing for a 60 Hz, 640x480 VGA Display
- VGA Signal Timing
- Keyboard
- Mouse
- Voltage Supply
- SPI Communication
- Interface Signals
- SPI Communication Details
- Specifying the DAC Output Voltage
- Digital Outputs from Analog Inputs
- Programmable Pre-Amplifier
- SPI Control Interface
- Disable Other Devices on the SPI Bus to Avoid Contention
- StrataFlash Connections
- Shared Connections
- Control
- Configuring from SPI Flash
- Creating an SPI Serial Flash PROM File
- Formatting an SPI Flash PROM File
- Downloading the Design to SPI Flash
- Insert Jumper on JP8 and Hold PROG_B Low
- Programming the SPI Flash with the XSPI Software
- Additional Design Details
- Other SPI Flash Control Signals
- Related Resources
- ddr sdram
- DDR SDRAM Connections
- Ethernet PHY Connections
- MicroBlaze Ethernet IP Cores
- Hirose 100-pin FX2 Edge Connector (J3)
- Voltage Supplies to the Connector
- Compatible Board
- Using Differential Inputs
- Using Differential Outputs
- Six-Pin Accessory Headers
- Header J4
- Connectorless Debugging Port Landing Pads (J6)
- Chapter 16: XC2C64A CoolRunner-II CPLD
- FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header
- RS-232 Ports, VGA Port, and PS/2 Port
- Ethernet PHY, Magnetics, and RJ-11 Connector
- Voltage Regulators
- FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections
- FPGA I/O Banks 0 and 1, Oscillators
- Power Supply Decoupling
- XC2C64A CoolRunner-II CPLD
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120 www.xilinx.com Spartan-3E Starter Kit Board User GuideUG230 (v1.0) March 9, 2006Chapter 15: Expansion Connectors RFigure 15-7: UCF Location Constraints for Accessory Headers# ==== FX2 Connector (FX2) ====NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;# These four connections are shared with the J1 6-pin accessory headerNET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;# These four connections are shared with the J2 6-pin accessory headerNET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;# These four connections are shared with the J4 6-pin accessory headerNET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;# The discrete LEDs are shared with the following 8 FX2 connections#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; PreviousNext |