Spartan-3E Starter Kit Board User Guide www.xilinx.com 23UG230 (v1.0) March 9, 2006Related ResourcesRClock Period ConstraintsThe Xilinx ISE development software uses timing-driven logic placement and routing. Setthe clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, whichequates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to60%.Related Resources• Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/prog_oscillators/go/Resources/TestC2/SG8002JFFigure 3-2: UCF Location Constraints for Clock SourcesNET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;Figure 3-3: UCF Clock PERIOD Constraint# Define clock period for 50 MHz oscillatorNET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
