Xilinx Virtex-5 FPGA ML561 User Manual

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10 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Preface: About This Guide RHardware MeasurementsThese measurements are the actual real-time measurements of an eye diagram and asegment of the test pattern (PRBS6) waveform captured on ML561 hardware at thedesignated probe point using an Agilent scope.Inter-Symbol Interference(ISI)As the frequency of operation increases, the signal delay is affected by the data patternthat precedes the current data bit. This is called the inter-symbol interference (ISI) effect.All testing is performed with a pseudo-random bitstream (PRBS) of order 6, that is,PRBS6. ISI is the jitter represented by the eye at all four voltage thresholds. The worstof the following two sum values are listed in this table:• Sum of ISI at VIH(ac)-min and VIH(dc)-min• Sum of ISI at VIL(ac)-max and VIL(dc)-maxNoise MarginThis is the noise margin available at the receiver. Measurements are taken at the ACvoltage levels as the minimum vertical opening of the eye in the vicinity of the centerof the bit period. Ideally, the input voltage needs to remain above the DC voltagespecifications. However, by considering the AC voltage specifications for the nominalvoltage level for VREF, these measurements are more conservative values that alsoinclude the effects of VREF variations.• VIH margin: Difference between the top of the eye opening and VIH(ac)-min• VIL margin: Difference between VIL(ac)-max and the bottom of the eye openingThese measurements are performed in stand-alone fashion for the signal under test.Thus no consideration of crosstalk or Simultaneously Switching Output (SSO) effectsare accounted for.Overshoot / UndershootMarginOvershoot margin is the difference between the maximum allowable VIH per JEDECspecification and the maximum amplitude of the measured eye. Similarly, undershootmargin is the difference between the minimum amplitude of the measured eye and theminimum allowable VIL value per JEDEC specification. For both SSTL18 and 1.8VHSTL specifications:• VIH(max) < (VDDQ + 300 mV) = (1.8 + 0.3)V = 2.1V• VIL(min) > -300 mV = 0.3VNote: VIH(max) must not exceed 1.9V for all Micron Parts.Simulation CorrelationThe BoardSim utility of the HyperLynx simulator is used to extract the IBIS schematicsof the same signal net for which hardware measurements are made. To replicate thehardware measurement probe set up at the probe point, a 0.5 pF probe capacitance isadded based on Agilent probe loading specifications to the extracted IBIS schematics ofthe memory signal. For the FPGA devices soldered on the ML561 board under test, theprocess corner (slow, typical, or fast) is not known. Thus simulation is performed for allthree corners (slow-weak, typical, and fast-strong), and the results of the case that bestfits with hardware measurement is selected for tabulation.VIH(ac)-min This term is the minimum input level at which the receiver must recognize input logicHigh.VIH(dc)-minWhen the input signal reaches VIH(ac)-min, the receiver continues to interpret theinput as a logic High as long as the signal remains above this voltage. (This parameteris basically the hysteresis for a logic ‘1’.)VIL(ac)-max This term is the maximum input level at which the receiver must recognize input logicLow.VIL(dc)-maxWhen the input signal reaches VIL(ac)-max, the receiver continues to interpret the inputas a logic Low as long as the signal remains below this voltage. (This parameter isbasically the hysteresis for logic ‘0’.)