Virtex-5 FPGA ML561 User Guide www.xilinx.com 7UG199 (v1.2.1) June 15, 2009RPrefaceAbout This GuideThis user guide describes the Virtex®-5 FPGA ML561 Memory Interfaces DevelopmentBoard. Complete and up-to-date documentation of the Virtex-5 family of FPGAs isavailable on the Xilinx website at http://www.xilinx.com/virtex5.Guide ContentsThis manual contains the following chapters:• Chapter 1, “Introduction”• Chapter 2, “Getting Started”• Chapter 3, “Hardware Description”• Chapter 4, “Electrical Requirements”• Chapter 5, “Signal Integrity Recommendations”• Chapter 6, “Configuration”• Chapter 7, “ML561 Hardware-Simulation Correlation”• Appendix A, “FPGA Pinouts”• Appendix B, “Bill of Materials”• Appendix C, “LCD Interface”Additional DocumentationThe following documents are also available for download athttp://www.xilinx.com/virtex5.• Virtex-5 Family OverviewThe features and product selection of the Virtex-5 family are outlined in this overview.• Virtex-5 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and Switching Characteristic specifications for theVirtex-5 family.• Virtex-5 FPGA User GuideChapters in this guide cover the following topics:- Clocking Resources- Clock Management Technology (CMT)- Phase-Locked Loops (PLLs)- Block RAM
