Xilinx Virtex-5 FPGA ML561 User Manual

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Contents

58 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation Correlation R♦ DDR2 mask (for nominal VDDQ = 1.8V and VREF = 0.9V):- VIH(ac)-min = VREF + 200 mV = 1.1V- VIH(dc)-min = VREF + 125 mV = 1.025V- VIL(ac)-max = VREF – 200 mV = 0.7V- VIL(dc)-max = VREF – 125 mV = 0.775V♦ QDRII mask (for nominal values of VDDQ = 1.8V and VREF = 0.9V):- VIH(ac)-min = VREF + 200 mV = 1.1V- VIH(dc)-min = VREF + 100 mV = 1.0V- VIL(ac)-max = VREF – 200 mV = 0.7V- VIL(dc)-max = VREF – 100 mV = 0.8VSignal Integrity Correlation ResultsThis section presents SI results for each of the six chosen memory signals on the ML561board. The following information is presented for each memory signal:• A post-layout IBIS schematics of the signal under test• A description of the major circuit elements (1) of this signal• A summary of four SI results: hardware measurement, correlation simulation, slow-weak corner driver simulation extrapolation, and fast-strong corner driver simulationextrapolation• A set of eight figures showing eye and waveform scope shots for each of the four SIresults mentioned in the bulleted list in the previous sectionFor an explanation of the different terms used to present these results, refer to“Terminology,” page 9 for some definitions and routing terminologies.Figure 7-2: Two Triangular Eye Mask Definitions for VIH and VILVOH(dc)VOL(dc)VOH(ac)VOL(ac)UG199_c7_02_062707VIH(ac)VIL(ac)VIH(dc)VIL(dc)VDDQVSSVREF1. With regard to transmission line impedance, Table 3-19 in the “Board Design Considerations” section listscontrolled impedance values of all routing layers. The design goal for the ML561 board is to keep thecharacteristic impedance for all routing layers as close to 50Ω as possible. Manufacturing tolerance is usually±10%. The characteristic impedance of DIMM PCB is derived from the Micron DIMM layout file.