Xilinx Virtex-5 FPGA ML561 User Manual
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76 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation Correlation RDDR2 DIMM Read OperationThis subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from theDDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), where the unitinterval (UI) = 1.5 ns.To perform hardware measurements for a Read operation that is not interrupted by a Writeor a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch(SW1) setting:• DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabledFigure 7-30: Post-Layout IBIS Schematics of the DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_B)59.8 ohms78.962 ps0.490 inMDQ19_B0159.8 ohms31.503 ps0.195 inMDQ19_B0159.8 ohms3.590 ps0.022 inMDQ19_B01TL11TL1U3_B01.J1TL5 22.0 ohmsRN6_B01MT47H64M8CB_C...DQ6C13500.0 fF17.3 fFMDQ19_...59.8 ohms10.373 ps0.064 inDQ19_B01TL12J1_B01.31????49.8 ohms94.605 ps0.606 inDDR2_DIMM_DQ_...49.8 ohms90.955 ps0.582 inDDR2_DIMM_DQ_...49.8 ohms90.340 ps0.578 inDDR2_DIMM_DQ_...49.8 ohms864.365 ps5.533 inDDR2_DIMM_DQ_...59.1 ohms12.486 psAutoPadstk_12_B...TL15 TL16 TL17 TL18 TL19XP5_B00.31XP4_B00.31XP3_B00.31XP2_B00.31TL25TL23TL27TL14????????????????50.3 ohms23.650 psDDR2_D...50.3 ohms23.650 psDDR2_D...50.3 ohms23.650 psDDR2_D...50.3 ohms23.650 psDDR2_D...0.0 milliohms 0.0 milliohms 0.0 milliohms 0.0 milliohmsR_00179... R7 R5 R6DDR2_DI...253.0 fF50.3 ohms23.650 psDQ19_B...50.3 ohms23.650 psDQ19_B...50.3 ohms23.650 psDQ19_B...50.3 ohms23.650 psDQ19_B...TL24TL22TL26TL13DDR2_DI...DDR2_DI...DDR2_DI...500.0 fFC896.3 fF46.4 fF22.9 fFU5_B00.H29Virtex-5 FPGADIMM_DQ_BY2_B328.5 ohms4.473 ps0.028 inDDR2_DIMM_DQ_...49.1 ohms41.316 ps0.264 inDDR2_DIMM_DQ_...49.1 ohms78.216 ps0.501 inDDR2_DIMM_DQ_...71.6 ohms22.319 psAutoPadstk_3_B00TL3TL6TL7TL20UG199_c7_30_071907Table 7-9: Circuit Elements of DDR2 DIMM Read Data Bit(DDR2_DIMM_DQ_BY2_B3)Element Designation DescriptionDriver XP2-U3.J1 DDR2 DIMMReceiver U5.H29 FPGA SSTL18_II_DCI_IProbe Point C8 Via under FPGA2 (U5.H29)PCB Termination None DCI at loadTrace Length Multiple TLs 8.975 inchesTable 7-10: DDR2 DIMM Read Operation Correlation ResultsMeasurement DVW (%UI)ISI(% UI)Noise Margin(VIH + VIL) = Total(% of VREF)Overshoot / UndershootMargin(% of VREF)Hardware at probepoint904 ps(60%)(107 + 62) = 169 ps(11.2%) (242 + 258) = 500 mV (623 + 613) = 1236 mV(137.3%)Simulation correlationslow-weak corner865 ps(59%)(130 + 83) = 213 ps(14.2%) (+292 + 298) = 590 mV (524 + 504) = 1028 mV(114.2%)Correlation Delta:HW vs. Simulation39 ps(2.6%) 44 ps (2.9%) 90 mV (10%) 208 mV (23.1%)Extrapolation at IOBslow-weak corner1.23 ns(82%)(139 + 75) = 224 ps(14.9%)(243 + 303) = 546 mV(60.7%)(594 + 544) = 1138 mV(116.5%)Extrapolation at IOBfast-strong corner1.24 ns(83%)(131 + 60) = 191 ps(12.7%)(288 + 282) = 570 mV(63.3%)(+481 + 508) = 989 mV(109.9%) |
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