Xilinx Virtex-5 FPGA ML561 User Manual Manual pdf 68 page image
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Xilinx Virtex-5 FPGA ML561 User Manual

Also see for Virtex-5 FPGA ML561: User guideUser guideUser guideUser guideUser guide

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Contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Guide Contents
  6. Additional Support Resources
  7. Conventions
  8. About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit
  9. Virtex-5 FPGA ML561 Memory Interfaces Development Board
  10. Documentation and Reference Design CD
  11. Applying Power to the Board
  12. Hardware Overview
  13. FPGA
  14. Memories
  15. DDR2 SDRAM Components
  16. Memory Details
  17. DDR2 SDRAM DIMM
  18. QDRII and RLDRAM II Memories
  19. External Interfaces
  20. MHz LVPECL Clock
  21. MHz System ACE Controller Oscillator
  22. Seven-Segment Displays
  23. Power On or Off Slide Switch
  24. Liquid Crystal Display Connector
  25. Power Regulation
  26. Voltage Regulators
  27. Board Design Considerations
  28. Power Consumption
  29. FPGA Internal Power Budget
  30. Termination and Transmission Line Summaries
  31. Configuration Modes
  32. JTAG Chain
  33. Introduction
  34. Test Setup
  35. Signal Integrity Correlation Results
  36. DDR2 Component Write Operation
  37. DDR2 Component Read Operation
  38. DDR2 DIMM Write Operation
  39. DDR2 DIMM Read Operation
  40. QDRII Write Operation
  41. QDRII Read Operation
  42. Summary and Recommendations
  43. How to Generate a User-Specific FPGA IBIS Model
  44. FPGA #1 Pinout
  45. FPGA #2 Pinout
  46. FPGA #3 Pinout
  47. bill of materials
  48. General
  49. Hardware Schematic Diagram
  50. Peripheral Device KS0713
  51. Controller – Operation
  52. Controller – LCD Panel Connections
  53. Controller – Power Supply Circuits
  54. Operation Example of the 64128EFCBC-3LP
  55. Instruction Set
  56. Read/Write Characteristics (6800 Mode)
  57. Design Examples
  58. LCD Panel Used in Character Mode
  59. Array Connector Numbering
Xilinx Virtex-5 FPGA ML561 User Manual Manual pdf 68 page image
68 www.xilinx.com Virtex-5 FPGA ML561 User GuideUG199 (v1.2.1) June 15, 2009Chapter 7: ML561 Hardware-Simulation Correlation RFigure 7-17: DDR2 Component Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)800.0 1200.0 1600.0 2000.0 2400.0 2800.0-100.0100.0300.0500.0700.0900.01100.01300.01500.01700.01900.0UG199_c7_17_071007Time (ps)Voltage (mV)Probe 1:U7.P25 (at die)♦ 333 MHz, Slow, PRBS6, 85.5% UI♦ Cursor 1: 1.0988V, 1.2170 ns♦ Cursor 2: 1.0254V, 2.5029 ns♦ Delta Voltage = 73.4 mV, Delta Time = 1.2859 ns (85.5% UI)Figure 7-18: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)-200.00.000200.0400.0600.0800.01000.01200.01400.01600.01800.065.000 75.000 85.000 95.000 105.000Probe 1:U7.P25 (at die)Voltage (mV)Time (ns) UG199_c7_18_071007
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Virtex-5 FPGA ML561
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