Xilinx Virtex-5 FPGA ML561 User Manual

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Contents

Virtex-5 FPGA ML561 User Guide www.xilinx.com 119UG199 (v1.2.1) June 15, 2009RAppendix CLCD InterfaceThis appendix describes the LCD interface for the Virtex-5 FPGA ML561 DevelopmentBoard.GeneralThe Virtex-5 FPGA ML561 Development Board has a full graphical LCD panel. Thisdisplay was chosen because of its possible use in embedded systems. A character-typedisplay also can be connected because the graphical LCD has the same interface as thecharacter-type LCD panels.A hardware character generator must be designed to display characters on the screen.Display Hardware DesignThe FPGA (I/O functioning at 2.5V) is connected to the graphic LCD panel through a set ofvoltage-level converting devices. These switches translate the 2.5 I/O voltage to a 3.3Vvoltage for the LCD panel.A graphics-based LCD panel from DisplayTech (64128EFCBC-XLP) is used on the Virtex-5FPGA ML561 Development Board. The control for this LCD panel is based on the KS0713controller from Samsung. The KS0713 is a 65-column, 132-segment driver-controller devicefor graphic dot matrix LCD systems. The chip accepts serial or parallel display data. The8-bit parallel interface is compatible with most LCD panel manufacturers. The serialconnection mode is write only.Extra features added to the interface in addition to the normal parallel signals are:• Intel or Motorola compatible interface• External reset of the chip• External chip selectThe interface also contains the following built-in options for the display and controller:• On-chip oscillator circuitry• On-chip voltage converter (x2, x3, x4, and x5)• A 64-step electronic contrast control function