Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 125UG366 (v2.5) January 17, 2011ACJTAGTable 2-17 defines the loopback attributes.ACJTAGFunctional DescriptionThe Virtex-6 FPGA GTX transceiver supports ACJTAG, as specified by IEEE Std 1149.6. Toensure reliable ACJTAG operation, the GTX RX expects the swing coming in to be800 mV PPD (400 mVPPSE) or higher. In ACJTAG mode, the GTX TX swing is nominally800 mV PPD . For JTAG clock operating frequencies specifically in ACJTAG mode, refer tothe Virtex-6 FPGA Data Sheet.Dynamic Reconfiguration PortFunctional DescriptionThe dynamic reconfiguration port (DRP) allows the dynamic change of parameters of theGTXE1 primitive. The DRP interface is a processor-friendly synchronous interface with anaddress bus (DADDR) and separated data buses for reading (DRPDO) and writing (DI)configuration data to the GTXE1 primitive. An enable signal (DEN), a read/write signal(DWE), and a ready/valid signal (DRDY) are the control signals that implement read andwrite operations, indicate operation completion, or indicate the availability of data. Referto the Virtex-6 FPGA Configuration User Guide for detailed descriptions and timingdiagrams of the DRP operations. Refer to Appendix B, DRP Address Map of the GTXTransceiver, for a DRP map of the GTX transceiver attributes.Table 2-16: Loopback PortsPort Dir ClockDomain DescriptionLOOPBACK[2:0] In Async 000: Normal operation001: Near-End PCS Loopback010: Near-End PMA Loopback011: Reserved100: Far-End PMA Loopback101: Reserved110: Far-End PCS LoopbackTable 2-17: Loopback AttributesPort Type DescriptionTXDRIVE_LOOPBACK_HIZ Boolean Reserved. Use only recommended valuesfrom the Virtex-6 FPGA GTX TransceiverWizard.TXDRIVE_LOOPBACK_PD Boolean Reserved. Use only recommended valuesfrom the Virtex-6 FPGA GTX TransceiverWizard.www.BDTIC.com/XILINX
