Xilinx Virtex-6 FPGA User Manual

Also see for Virtex-6 FPGA: User guide Guide Hardware setup guide User guide User guide

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Xilinx Virtex-6 FPGA User Manual Manual pdf 192 page image

192 www.xilinx.com Virtex-6 FPGA GTX Transceivers User GuideUG366 (v2.5) January 17, 2011Chapter 4: ReceiverRX Out-of-Band SignalingFunctional DescriptionThe GTX receiver provides support for decoding the Out-of-Band (OOB) sequencesdescribed in the Serial ATA (SATA) and Serial Attach SCSI (SAS) specifications andsupports beaconing described in the PCI Express specification. GTX receiver support forSATA/SAS OOB signaling consists of the analog circuitry required to decode the OOBsignal state and state machines to decode bursts of OOB signals for SATA/SAS COMsequences.The GTX receiver also supports beacons that are PCI Express compliant by using interfacesignals defined in the PHY Interface for the PCI Express (PIPE) Specification. The FPGA logicdecodes the beacon sequence.Ports and AttributesTable 4-9 defines the RX OOB ports.Table 4-9: RX OOB PortsPort Direction Clock Domain DescriptionCOMINITDET Out RXUSRCLK2 Indicates detection of a COMINIT sequence.COMSASDET Out RXUSRCLK2 Indicates detection of a COMSAS sequence.COMWAKEDET Out RXUSRCLK2 Indicates detection of a COMWAKE sequence.GATERXELECIDLE In Async Optional port. This port is tied to zero for PCIe and SATAmodes (default). For other usages, this port is asserted High togate the RXELECIDLE output (see Figure 4-8).IGNORESIGDET In Async Optional port. This port is tied to zero for PCIe and SATAmodes (default). For other usages, this port is asserted High todisable RX signal electrical idle detection logic from resettingother GTX transceivers logic, including comma detection, RXelastic buffer logic, and DFE logic (see Figure 4-8). WhenIGNORESIGDET is set High, it prevents the followingattributes from automatically triggering an internal reset orhold on RX electrical idle:• RX_EN_IDLE_RESET_BUF• RX_EN_IDLE_HOLD_CDR• RX_EN_IDLE_RESET_FR• RX_EN_IDLE_RESET_PH• RX_EN_IDLE_HOLD_DFERXELECIDLE Out Async Indicates the differential voltage between RXN and RXPdropped below the minimum threshold(OOBDETECT_THRESHOLD). Signals below this threshold areOOB signals.1: OOB signal detected. The differential voltage is below theminimum threshold.0: OOB signal not detected. The differential voltage is abovethe minimum threshold.This port is intended for PCI Express and SATA standards.www.BDTIC.com/XILINX