Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 39UG366 (v2.5) January 17, 2011SimulationSIM_GTXRESET_SPEEDUPThe SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time ofthe TX PMA PLL and the RX PMA PLL.SIM_RXREFCLK_SOURCE 3-Bit Binary This attribute selects the reference clock source used to drive the RXPMA PLL in simulation for designs where the RX PMA PLL isalways driven by the same reference clock source. TheRXPLLREFSELDY port must be set to 000 for this attribute to selectthe reference clock source. For multi-rate designs that require thereference clock source to be changed on the fly, theRXPLLREFSELDY port is used to dynamically select the sourceinstead.000: Selects the MGTREFCLKRX[0] port as the source001: Selects the MGTREFCLKRX[1] port as the source010: Selects the NORTHREFCLKRX[0] port as the source011: Selects the NORTHREFCLKRX[1] port as the source100: Selects the SOUTHREFCLKRX[0] port as the source101: Selects the SOUTHREFCLKRX[1] port as the source110: Reserved111: Selects a clock from the FPGA logic which can be either portGREFCLKRX or PERFCLKRX as the sourceSIM_TX_ELEC_IDLE_LEVEL 1-Bit Binary This attribute sets the value of TXN and TXP during simulation ofelectrical idle. This attribute can be set to 0, 1, x, or z. The default forthis attribute is x.SIM_TXREFCLK_SOURCE 3-Bit Binary This attribute selects the reference clock source used to drive the TXPMA PLL in simulation for designs where the TX PMA PLL isalways driven by the same reference clock source. TheTXPLLREFSELDY port must be set to 000 for this attribute to selectthe reference clock source. For multi-rate designs that require thereference clock source to be changed on the fly, theTXPLLREFSELDY port is used to dynamically select the sourceinstead.000: Selects the MGTREFCLKTX[0] port as the source001: Selects the MGTREFCLKTX[1] port as the source010: Selects the NORTHREFCLKTX[0] port as the source011: Selects the NORTHREFCLKTX[1] port as the source100: Selects the SOUTHREFCLKTX[0] port as the source101: Selects the SOUTHREFCLKTX[1] port as the source110: Selects the RX recovered clock from the RX channel as thesource111: Selects a clock from the FPGA logic that can be either theGREFCLKTX or the PERFCLKTX port as the sourceSIM_VERSION Real This attribute selects the simulation version to match differentsteppings of silicon. The default for this attribute is 1.0.Table 1-2: GTXE1 Simulation-Only Attributes (Cont’d)Attribute Type Descriptionwww.BDTIC.com/XILINX
