268 www.xilinx.com Virtex-6 FPGA GTX Transceivers User GuideUG366 (v2.5) January 17, 2011Chapter 4: ReceiverAfter Connecting RXN/RXPWhen the RX data to the GTX transceiver comes from a connector that can be plugged inand unplugged, the RX CDR must be reset when the data source is plugged in to ensurethat it can lock to incoming data. When the guidelines in Link Idle Reset Support, page 264are followed, the electrical idle reset situation is automatically managed.After an RX Elastic Buffer ErrorAfter an RX elastic buffer overflow or underflow, the RX elastic buffer must be reset usingthe RXBUFRESET port to ensure correct behavior.Before Channel BondingFor successful channel bonding, the RX elastic buffers of all the bonded transceivers mustbe written using the same recovered frequency, and read using the same RXUSRCLKfrequency.To provide RXUSRCLK of the same frequency to all bonded transceivers, a low-skew clockbuffer (for example, a BUFG) must be used to drive all the RXUSRCLK ports from the sameclock source. Bonding should not be attempted until the clock source is stable.To provide the same recovered clock to all bonded transceivers:• All TX data sources must be locked to the same reference clock.• All bonded transceivers must have CDR lock to the incoming data.The required reset for channel bonding is:• To automatically reset the CDR of all bonded transceivers, setRX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR, andRX_EN_IDLE_HOLD_CDR to TRUE.• Wait for CDR lock and bit alignment on all bonded transceivers.• Either assert RXBUFRESET to all bonded transceivers or, for an automatic reset, setRX_EN_IDLE_RESET_BUF = TRUE to enable the RXBUFRESET sequence.• Attempt channel bonding.See RX CDR, page 204 for recommendations on how to detect CDR lock.After Changing Channel Bonding Mode on the FlyWhen set to TRUE, RX_EN_MODE_RESET_BUF enables automatic reset of the RX elasticbuffer when the RXCHANBONDMASTER, RXCHANBONDSLAVE, orRXCHANBONDLEVEL ports change. See RX Channel Bonding, page 247.After a PRBS ErrorPRBSCNTRESET is asserted to reset the PRBS error counter.After an Oversampler ErrorIf RXOVERSAMPLEERR goes High to indicate an overflow or underflow in theoversampling block FIFO, asserting RXRESET clears it.www.BDTIC.com/XILINX
