Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 247UG366 (v2.5) January 17, 2011RX Channel BondingRX Channel BondingFunctional DescriptionThe RX elastic buffer can also be used for channel bonding. Channel bonding cancels outthe skew between GTX transceiver lanes by using the RX elastic buffer as a variable latencyblock. The transmitter sends a pattern simultaneously on all lanes, which the channelbonding circuit uses to set the latency for each lane so that data is presented without skewat the FPGA RX interface.Figure 4-38 shows a conceptual view of channel bonding.Ports and AttributesTable 4-48 defines the RX channel bonding ports.X-Ref Target - Figure 4-38Figure 4-38: Channel Bonding Conceptual ViewDeskewed DataRX Data is Two Clock CyclesBehind GTX0 Data64 Element Elastic Buffer(Set to Two Cycles of Latency byChannel Bonding Controller)UG366_c4_35_051509GTX1 (Slave)Deskewed DataRX Data is Two Clock CyclesAhead of GTX1 Data64 Element Elastic Buffer(Set to Four Cycles of Latency byChannel Bonding Controller)GTX0 (Master)Table 4-48: RX Channel Bonding PortsPort Dir Clock Domain DescriptionRXCHANBONDSEQ Out RXUSRCLK2 This port goes High when RXDATA contains the start of achannel bonding sequence.RXCHANISALIGNED Out RXUSRCLK2 This signal from the RX elastic buffer goes High to indicate thatthe channel is properly aligned with the master transceiveraccording to observed channel bonding sequences in the datastream. This signal goes Low if an unaligned channel bondingsequence is detected, indicating that channel alignment waslost.www.BDTIC.com/XILINX
