274 www.xilinx.com Virtex-6 FPGA GTX Transceivers User GuideUG366 (v2.5) January 17, 2011Chapter 5: Board Design GuidelinesFigure 5-1 shows the connections of the power supply pins for the GTX transceiver. Thelisted voltages are nominal values. Refer to the Virtex-6 FPGA Data Sheet for values andoperating conditions.Termination Resistor Calibration CircuitOne resistor calibration circuit (RCAL) is shared between all of the Quad primitives in aQuad column (see Figure 5-2). The MGTAVTTRCAL and MGTRREF pins are used toconnect the bias circuit power and the external calibration resistor to the RCAL circuit. TheRCAL circuit performs the resistor calibration only during configuration of the FPGA.Prior to configuration, all analog supply voltages must be present and within the propertolerance as specified in the Virtex-6 FPGA Data Sheet.The RCAL circuit is associated with the MGT115 Quad. It is referred to as the RCALMaster. The RCAL Master performs the termination resistor calibration duringconfiguration of the FPGA and then distributes the calibrated values to all of the Quads inthe column.MGTRXP0/MGTRXN0MGTRXP1/MGTRXN1MGTRXP2/MGTRXN2MGTRXP3/MGTRXN3In(Pad)RXP and RXN are the differential input pairs for each of the receivers in the Quad.MGTTXP0/MGTTXN0MGTTXP1/MGTTXN1MGTTXP2/MGTTXN2MGTTXP3/MGTTXN3Out(Pad)TXP and TXN are the differential output pairs for each of the transmitters in theQuad.Table 5-1: Quad Pin Descriptions (Cont’d)Pin Dir DescriptionX-Ref Target - Figure 5-1Figure 5-1: Virtex-6 FPGA GTX Transceiver Power Supply ConnectionsQuadGTX Column RCALMGTAVCCMGTAVTTMGTAVTTRCAL100 ohm1.2V1.0VMGTRREFUG366_c5_01_051809www.BDTIC.com/XILINX
