LAPIS Semiconductor ML610Q174 manuals
ML610Q174
Table of contents
- FEUL610Q174
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Overview
- Configuration of Functional Blocks
- Pins
- List of Pins
- Pin Description
- Termination of Unused Pins
- CPU and Memory Space
- Data Memory Space
- Instruction Length
- Description of Registers
- Data Segment Register (DSR)
- Reset Function
- Description of Operation
- MCU Control Function
- Stop Code Acceptor (STPACP)
- Standby Control Register (SBYCON)
- Block Control Register 0 (BLKCON0)
- Block Control Register 2 (BLKCON2)
- Block Control Register 4 (BLKCON4)
- Block Control Register 6 (BLKCON6)
- Block Control Register 7 (BLKCON7)
- STOP Mode
- STOP Mode When CPU Operates with High-Speed Clock
- Note on Return Operation from STOP/HALT Mode
- Block control function
- Interrupts (INTs)
- Interrupt Enable Register 0 (IE0)
- Interrupt Enable Register 1 (IE1)
- Interrupt Enable Register 2 (IE2)
- Interrupt Enable Register 3 (IE3)
- Interrupt Enable Register 4 (IE4)
- Interrupt Enable Register 5 (IE5)
- Interrupt Enable Register 6 (IE6)
- Interrupt Enable Register 7 (IE7)
- Interrupt Request Register 0 (IRQ0)
- Interrupt Request Register 1 (IRQ1)
- Interrupt Request Register 2 (IRQ2)
- Interrupt Request Register 3 (IRQ3)
- Interrupt Request Register 4 (IRQ4)
- Interrupt Request Register 5 (IRQ5)
- Interrupt Request Register 6 (IRQ6)
- Interrupt Request Register 7 (IRQ7)
- Maskable Interrupt Processing
- Notes on Interrupt Routine
- Interrupt Disable State
- port.
- Frequency Control Register 0(FCON0)
- Frequency Control Register 1 (FCON1)
- Frequency Status Register (FSTAT)
- External Interrupt
- High-Speed Clock
- High-Speed External Clock Input Mode
- Operation of High-Speed Clock Generation Circuit
- Switching of System Clock
- Register setup of the port
- When the P20 pin (LSCLK:output) operates as the low-speed clock output function
- When the P36 pin (LSCLK:output) operates as the low-speed clock output function
- Time Base Counter
- Low-Speed Time Base Counter (LTBR)
- High-Speed Time Base Counter Divide Register (HTBDR)
- High-Speed Time Base Counter
- Low-Speed Time Base Counter Frequency Adjustment Function
- Timers
- Timer 0 Data Register (TM0D)
- Timer 1 Data Register (TM1D)
- Timer 8 Data Register (TM8D)
- Timer 9 Data Register (TM9D)
- Timer A Data Register (TMAD)
- Timer B Data Register (TMBD)
- Timer 0 Counter Register (TM0C)
- Timer 1 Counter Register (TM1C)
- Timer 8 Counter Register (TM8C)
- Timer 9 Counter Register (TM9C)
- Timer A Counter Register (TMAC)
- Timer B Counter Register (TMBC)
- Timer 0 Control Register 0 (TM0CON0)
- Timer 1 Control Register 0 (TM1CON0)
- Timer 8 Control Register 0 (TM8CON0)
- Timer 9 Control Register 0 (TM9CON0)
- Timer A Control Register 0 (TMACON0)
- Timer B Control Register 0 (TMBCON0)
- Timer 0 Control Register 1 (TM0CON1)
- Timer 1 Control Register 1 (TM1CON1)
- Timer 8 Control Register 1 (TM8CON1)
- Timer 9 Control Register 1 (TM9CON1)
- Timer A Control Register 1 (TMACON1)
- Timer B Control Register 1 (TMBCON1)
- Handling example when you do not want to use the watch dog timer
- Configuration
- PWM4 Period Registers (PW4PL, PW4PH)
- PWM4 Duty Registers (PW4DL, PW4DH)
- PWM4 Counter Registers (PW4CH, PW4CL)
- PWM4 Control Register 0 (PW4CON0)
- PWM4 Control Register 1 (PW4CON1)
- PWM4 Control Register 2 (PW4CON2)
- PWM4 Control Register 3 (PW4CON3)
- PWM5 Period Registers (PW5PL, PW5PH)
- PWM5 Duty Registers (PW5DL, PW5DH)
- PWM5 Counter Registers (PW5CH, PW5CL)
- PWM5 Control Register 0 (PW5CON0)
- PWM5 Control Register 1 (PW5CON1)
- PWM5 Control Register 2 (PW5CON2)
- PWM6 Period Registers (PW6PL, PW6PH)
- PWM6 Duty Registers (PW6DL, PW6DH)
- PWM6 Counter Registers (PW6CH, PW6CL)
- PWM6 Control Register 0 (PW6CON0)
- PWM6 Control Register 1 (PW6CON1)
- PWM6 Control Register 2 (PW6CON2)
- Repeat Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Not Used P45MD="1", P4DTMD="0", P4MD="0")
- Repeat Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Used P45MD="1", P4DTMD="1", P4MD="0")
- One-shot Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Used P45MD="1", P4DTMD="1", P4MD="1")
- Software Start Mode
- External Input Start Mode
- Software Start or External Input Clear Mode
- Emergency Stop Operation
- Specifying Port Registers
- Functioning P43 Pin (PWM4) as PWM Output
- Functioning P35 Pin (PWM5) as PWM Output
- Functioning P47 Pin (PWM5) as PWM Output
- Functioning P53 Pin (PWM6) as PWM Output
- Synchronous Serial Port
- Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)
- Serial Port Transmit/Receive Buffers (SIO1BUFL, SIO1BUFH)
- Serial Port Control Register (SIO0CON)
- Serial Port Control Register (SIO1CON)
- Serial Port Mode Register 0 (SIO0MOD0)
- Serial Port Mode Register 0 (SIO1MOD0)
- Serial Port Mode Register 1 (SIO0MOD1)
- Serial Port Mode Register 1 (SIO1MOD1)
- Receive Operation
- Transmit/Receive Operation
- UART
- UART0 Transmit/Receive Buffer (UA0BUF)
- UART0 Control Register (UA0CON)
- UART0 Mode Register 0 (UA0MOD0)
- UART1 Mode Register 0 (UA1MOD0)
- UART0 Mode Register 1 (UA0MOD1)
- UART1 Mode Register 1 (UA1MOD1)
- UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)
- UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH)
- UART0 Status Register (UA0STAT)
- UART1 Status Register (UA1STAT)
- Baud Rate
- Transmit Data Direction
- Transmit Operation
- Detection of Start bit
- Reception Margin
- When operating the UART function using PF3 pin (TXD0:output) and PF2 pin (RXD0:input)
- When operating the UART function using PF7 pin (TXD1:output) and PF6 pin (RXD1:input)
- I2C Bu Interface
- I 2 C Bus 0 Control Register (I2C0CON)
- Communication Operation Timing
- I 2 C Bus 0 Status Register (I2C0STAT)
- Operation Waveforms
- Functioning P41(SCL) and P40(SDA) as the I2C
- Port 0 Control Registers 0, 1 (P0CON0, P0CON1)
- External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)
- External Interrupt Control Register 2 (EXICON2)
- Port 1 Data Register (P1D)
- Port 1 Control Registers 0,1 (P1CON0, P1CON1)
- Port 2 Data Register (P2D)
- Port 2 control registers 0, 1 (P2CON0, P2CON1)
- Port 2 Mode Register (P2MOD)
- Port 3 Direction Register (P3DIR)
- Port 3 control registers 0, 1 (P3CON0, P3CON1)
- Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1)
- Port 4 Direction Register (P4DIR)
- Port 4 Control Registers 0, 1 (P4CON0, P4CON1)
- Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1)
- Port 5 Direction Register (P5DIR)
- Port 5 Control Registers 0, 1 (P5CON0, P5CON1)
- Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1)
- Port 9 Data Register (P9D)
- Port 9 Control Registers 0, 1 (P9CON0, P9CON1)
- Port C Data Register (PCD)
- Port C Direction Register (PCDIR)
- Port C control registers 0, 1 (PCCON0, PCCON1)
- Secondary Function
- Port D Data Register (PDD)
- Port D Direction Register (PDDIR)
- Port D control registers 0, 1 (PDCON0, PDCON1)
- Port F Mode Registers 0, 1 (PFMOD0, PFMOD1)
- LCD Drivers
- Features
- Configuration of the LCD drive voltage control circuit
- Bias Circuit Control Register 0 (BIASCON)
- Display Mode Register 0 (DSPMOD0)
- Display Control Register (DSPCON)
- Bias circuit Mode Register 0 (BIASMOD)
- Display Registers (DSPR00 to DSPR17, DSPR20 to DSPR27)
- LCD port segment selection register 1 (LSELS1)
- LCD port segment selection register 2 (LSELS2)
- LCD port segment selection register 4 (LSELS4)
- LCD port common selection register 0 (LSELC0)
- Display Register Segment Map
- Built-in division resistance for LCD drive voltage generation
- Common Output Waveforms for 1/4 duty and 1/3 bias
- Segment Output Waveform for 1/4 duty and 1/3 bias
- Common Output Waveforms for 1/4 duty and 1/2 bias
- Segment Output Waveform for 1/4 duty and 1/2 bias
- Successive Approximation Type A/D Converter (SA-ADC)
- SA-ADC Result Register 0L (SADR0L)
- SA-ADC Result Register 1L (SADR1L)
- SA-ADC Result Register 2L (SADR2L)
- SA-ADC Result Register 3L (SADR3L)
- SA-ADC Result Register 4L (SADR4L)
- SA-ADC Result Register 5L (SADR5L)
- SA-ADC Result Register 6L (SADR6L)
- SA-ADC Result Register 7L (SADR7L)
- SA-ADC Result Register 8L (SADR8L)
- SA-ADC Result Register 9L (SADR9L)
- SA-ADC Result Register AL (SADRAL)
- SA-ADC Result Register BL (SADRBL)
- SA-ADC Control Register 0 (SADCON0)
- SA-ADC Control Register 1 (SADCON1)
- SA-ADC Mode Register 0 (SADMOD0)
- SA-ADC Mode Register 1 (SADMOD1)
- Operation of Successive Approximation Type A/D Converter
- Battery Level Detector
- Battery Level Detector Control Register 0 (BLDCON0)
- Battery Level Detector Control Register 1 (BLDCON1)
- Operation of Battery Level Detector
- Analog Comparator
- Comparator0 Control Register 0 (CMP0CON0)
- Comparator0 Control Registers 1 (CMP0CON1)
- Comparator1 Control Register 0 (CMP1CON0)
- Comparator0 Control Registers 1 (CMP1CON1)
- Interrupt Request
- Power Supply Circuit
- Flash Memory Programming
- Flash Address Register L,H (FLASHAL,H)
- Flash Data Register L,H (FLASHDL,H)
- Flash Control Register (FLASHCON)
- Flash Acceptor (FLASHACP)
- Flash Self Register (FLASHSLF)
- Flash Remap Register (REMAPADD)
- Block Erase Function
- Sector Erase Function
- word Write Function
- Remap function by software
- Remap function by hardware (external terminal)
- Notes in Use
- How to Connect the On-Chip Debug Emulator
- Code-Option
- Code-Option Register (CODEOP0)
- The method of a setup of Code-Option data
- Appendix A Registers
- Appendix C Electrical Characteristics
- Appendix D The example of an application circuit
- Appendix E Check List
- Secondary and Tertiary Functions
LAPIS Semiconductor categories
More LAPIS Semiconductor categories
manualsdatabase
Your AI-powered manual search engine