ML610Q174 User’s ManualChapter 12 UARTFEUL610Q174-01 12-1712.3 Description of Operation12.3.1 Transfer Data FormatIn the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8bits can be selected as data bit. For the parity bit, “with parity bit”, “without parity bit”, “even parity”, or “odd parity”can be selected. For the stop bit, “1 stop bit” or “2 stop bits” are available and for the transfer direction, “LSB first”or “MSB first” are available for selection. For serial input/output logic, positive logic or negative logic can beselected.All these options are set with the UARTn mode register (UAnMOD1).Figure 12-2 and Figure 12-3 show the positive logic input/output format and negative logic input/output format,respectively.Figure 12-2 Positive Logic Input/Output FormatFigure 12-3 Negative Logic Input/Output FormatStartbit 1 2 3 4 5 6 7 8 ParitybitData bit1 framey 1 frameMAX: 12 bitsMIN: 7 bitsy Data bit length 8 to 5 bits variabley Parity bit With or without parity bit selectableOdd or even parity selectabley Stop bit 1 or 2 stop bits selectableStopbitStopbitStartbit 1 2 3 4 5 6 7 8 ParitybitData bit1 frameStopbitStopbity 1 frameMAX: 12 bitsMIN: 7 bitsy Data bit length 8 to 5 bits variabley Parity bit With or without parity bit selectableOdd or even parity selectabley Stop bit 1 or 2 stop bits selectable
