ML610Q174 User’s ManualChapter 7 Time Base CounterFEUL610Q174-01 7-17. Time Base Counter7.1 OverviewThis LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generatebase clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically.For input clocks, see Chapter 6, “Clock Generation Circuit”. For interrupt permission, interrupt request flags, etc.,described in this chapter, see Chapter 5, “Interrupts”.7.1.1 Features• LTBC generates T32KHZ to T1HZ signals by dividing the low-speed clock (LSCLK) frequency.• Adjustment of the frequency by the low-speed time base counter frequency adjustment register (LTBADJH,LTBADJL) is possible for LTBC.(adjustment range: Approx -488ppm to +488ppm adjustment accuracy: Approx0.48 ppm)• HTBC generates HTB1 to HTB32 signals by dividing the high-speed clock (HSCLK) frequency.• Capable of generating 128Hz , 32Hz , 16Hz , and 2Hz interrupts.7.1.2 ConfigurationFigure 7-1 and Figure 7-2 show the configuration of a low-speed time base counter and a high-speed time base counter,respectively.LTBR: Low-speed time base counter registerLTBADJL: Low-speed time base counter frequency adjustment registerLTBADJH: High-speed time base counter frequency adjustment registerFigure 7-1 Configuration of Low-Speed Time Base Counter (LTBC)LSCLK(32.768kHz)7bits-CounterRLTBR8bits-CounterRRESET（Internal signal）LTBR WriteLTBADJLLTBDJH8Data busT2HZT4HZT8HZT16HZT32HZT64HZT128HZT256HZT512HZT1KHZT2KHZT4KHZT8KHZT16KHZT32KHZT1HZ8
