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mPD780205

Brand: NEC | Category: Microcontrollers
Table of contents
  1. User's Manual U11302EJ4V0UM
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. CHAPTER 1 OUTLINE
  17. Applications
  18. Pin Configuration (Top View)
  19. K/0 Series Lineup
  20. Block Diagram
  21. Overview of Functions
  22. Mask Options
  23. CHAPTER 2 PIN FUNCTIONS
  24. Description of Pin Functions
  25. P20 to P27 (Port
  26. P70 to P74 (Port
  27. 2.2.11 FIP0 to FIP12
  28. 2.2.12 V LOAD
  29. Pin I/O Circuits and Recommended Connection of Unused Pins
  30. Pin I/O Circuits
  31. CHAPTER 3 CPU ARCHITECTURE
  32. Memory Map ( µ PD780205 and µ PD780205A)
  33. Memory Map ( µ PD780206)
  34. Memory Map ( µ PD780208)
  35. Memory Map ( µ PD78P0208)
  36. Internal ROM Capacity
  37. Data memory addressing
  38. Data Memory Addressing ( µ PD780205 and µ PD780205A)
  39. Data Memory Addressing ( µ PD780206)
  40. Data Memory Addressing ( µ PD780208)
  41. Data Memory Addressing ( µ PD78P0208)
  42. Processor Registers
  43. Stack Pointer Format
  44. Data to Be Saved to Stack Memory
  45. General-purpose registers
  46. Special-function registers (SFRs)
  47. Special-Function Register List
  48. Instruction Address Addressing
  49. Immediate addressing
  50. Table indirect addressing
  51. Register addressing
  52. Operand Address Addressing
  54. Direct addressing
  55. Short direct addressing
  56. Special-function register (SFR) addressing
  57. Register indirect addressing
  58. Based addressing
  59. Based indexed addressing
  60. Port Functions
  62. Port Configuration
  63. Block Diagram of P00 and P04
  64. Port 1
  65. Port 2
  66. Block Diagram of P22 and P27
  67. Port 3
  68. Port 7
  69. Port 8
  70. Port 9
  71. Port 10
  72. Port 11
  73. Port 12
  74. Port Function Control Registers
  75. Format of Port Mode Register
  76. Format of Pull-up Resistor Option Register
  77. Port Function Operations
  78. Selection of Mask Option
  79. Clock Generator Functions
  80. Clock Generator Control Registers
  81. Format of Processor Clock Control Register
  82. Relationship Between CPU Clock and Minimum Instruction Execution Time
  83. Format of Display Mode Register 0
  84. Format of Display Mode Register 1
  85. System Clock Oscillator
  86. Subsystem clock oscillator
  87. Examples of Incorrect Resonator Connection
  88. Divider
  89. Clock Generator Operations
  90. Main system clock operations
  91. Subsystem clock operations
  92. Changing System Clock and CPU Clock Settings
  93. System clock and CPU clock switching procedure
  94. CHAPTER 6 16-BIT TIMER/EVENT COUNTER
  95. Bit Timer/Event Counter Functions
  96. Bit Timer/Event Counter Interval Time
  97. Bit Timer/Event Counter Configuration
  98. Bit Timer/Event Counter Control Registers
  99. Format of Timer Clock Select Register 0
  100. Format of 16-Bit Timer Mode Control Register
  101. Format of 16-Bit Timer Output Control Register
  102. Format of Port Mode Register 3
  103. Format of External Interrupt Mode Register
  104. Format of Sampling Clock Select Register
  105. Bit Timer/Event Counter Operations
  106. Interval Timer Operation Timing
  107. PWM output operations
  108. Pulse width measurement operations
  109. Configuration Diagram for Pulse Width Measurement in Free-Running Mode
  110. External event counter operation
  111. External Event Counter Configuration Diagram
  112. Square-wave output operation
  113. Bit Timer/Event Counter Operating Precautions
  114. Capture Register Data Retention Timing
  115. CHAPTER 7 8-BIT TIMER/EVENT COUNTER
  117. Bit Timer/Event Counter Square-Wave Output Ranges
  118. bit timer/event counter mode
  120. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
  122. Format of Timer Clock Select Register 1
  123. Format of 8-Bit Timer Mode Control Register
  124. Format of 8-Bit Timer Output Control Register
  127. Bit Timer/Event Counter 1 Interval Time
  128. External Event Counter Operation Timing (with Rising Edge Specified)
  129. Square-Wave Output Operation Timing
  134. Timing After Compare Register Change During Timer Count Operation
  135. CHAPTER 8 WATCH TIMER
  136. Watch Timer Configuration
  137. Format of Timer Clock Select Register 2
  138. Format of Watch Timer Mode Control Register
  139. Watch Timer Operations
  140. CHAPTER 9 WATCHDOG TIMER
  141. Watchdog Timer Configuration
  142. Watchdog Timer Control Registers
  144. Format of Watchdog Timer Mode Register
  145. Watchdog Timer Operations
  146. Interval timer operation
  147. CHAPTER 10 CLOCK OUTPUT CONTROLLER
  148. Clock Output Controller Configuration
  151. CHAPTER 11 BUZZER OUTPUT CONTROLLER
  152. Buzzer Output Function Control Registers
  155. CHAPTER 12 A/D CONVERTER
  156. A/D Converter Block Diagram
  157. A/D Converter Control Registers
  158. Format of A/D Converter Mode Register
  159. Format of A/D Converter Input Select Register
  160. A/D Converter Operations
  161. Basic Operation of A/D Converter
  162. Input voltage and conversion results
  163. A/D converter operating mode
  164. A/D Conversion by Software Start
  165. A/D Converter Precautions
  166. Analog Input Pin Processing
  167. A/D Conversion End Interrupt Request Generation Timing
  168. CHAPTER 13 SERIAL INTERFACE CHANNEL 0
  169. Functions of Serial Interface Channel 0
  170. Configuration of Serial Interface Channel 0
  171. Control Registers of Serial Interface Channel 0
  172. Format of Timer Clock Select Register 3
  173. Format of Serial Operating Mode Register 0
  174. Format of Serial Bus Interface Control Register
  175. Format of Interrupt Timing Specification Register
  176. Operations of Serial Interface Channel 0
  177. wire serial I/O mode operation
  178. Wire Serial I/O Mode Timing
  179. RELT and CMDT Operations
  180. SBI mode operation
  181. Example of Serial Bus Configuration with SBI
  182. SBI Transfer Timing
  183. Bus Release Signal
  184. Address
  185. Commands
  186. Acknowledge Signal
  187. BUSY and READY Signals
  188. RELT, CMDT, RELD, and CMDD Operations (Master)
  189. ACKT Operation
  190. ACKE Operations
  191. ACKD Operations
  192. Pin Configuration
  196. SCK0/P27 pin output manipulation
  197. CHAPTER 14 SERIAL INTERFACE CHANNEL 1
  198. Configuration of Serial Interface Channel 1
  199. Control Registers of Serial Interface Channel 1
  201. Format of Serial Operating Mode Register 1
  202. Format of Automatic Data Transmit/Receive Control Register
  203. Format of Automatic Data Transmit/Receive Interval Specification Register
  204. Operations of Serial Interface Channel 1
  207. Circuit for Switching Transfer Bit Order
  208. wire serial I/O mode operation with automatic transmit/receive function
  209. Basic Transmission/Reception Mode Operation Timing
  210. Basic Transmission/Reception Mode Flowchart
  211. Basic Transmission Mode Operation Timing
  212. Basic Transmission Mode Flowchart
  213. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode)
  214. Repeat Transmission Mode Operation Timing
  215. Repeat Transmission Mode Flowchart
  216. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)
  217. Automatic Transmission/Reception Suspension and Restart
  218. System Configuration with Busy Control Option
  219. Operation Timing When Using Busy Control Option (BUSY0 = 0)
  220. Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
  221. Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1)
  222. Automatic Transmit/Receive Interval
  223. Interval Determined by CPU Processing (with Internal Clock Operation)
  224. Interval Determined by CPU Processing (with External Clock Operation)
  225. CHAPTER 15 VFD CONTROLLER/DRIVER
  226. VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0)
  227. VFD Controller/Driver Configuration
  228. VFD Controller/Driver Control Registers
  231. Format of Display Mode Register 2
  232. One-display period and cut width
  233. Selecting Display Mode
  234. Display Mode and Display Output
  235. Display Data Memory
  236. Key Scan Flag and Key Scan Data
  237. Light Leakage of VFD
  238. Display Examples
  239. Segment type (display mode 1: DSPM05 = 0)
  240. Dot type (display mode 1: DSPM05 = 0)
  241. Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode
  242. Display Data Memory Configuration and Data Reading Order (Display Mode 2)
  243. Grid Driving Timing
  244. Calculating Total Power Dissipation
  245. Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode
  249. CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
  250. Interrupt Sources and Configuration
  251. Basic Configuration of Interrupt Function
  252. Interrupt Function Control Registers
  253. Format of Interrupt Request Flag Register
  254. Format of Interrupt Mask Flag Register
  255. Format of Priority Specification Flag Register
  258. Noise Eliminator I/O Timing (When Rising Edge Is Detected)
  259. Format of Program Status Word
  260. Interrupt Servicing Operations
  261. Non-Maskable Interrupt Request Acknowledgment Flowchart
  262. Non-Maskable Interrupt Request Acknowledgment Operation
  263. Maskable interrupt request acknowledgment operation
  264. Interrupt Request Acknowledge Processing Algorithm
  265. Software interrupt request acknowledgment operation
  266. Multiple interrupt servicing
  267. Multiple Interrupt Servicing Example
  268. Interrupt request hold
  269. Test Functions
  270. Test input signal acknowledgment operation
  271. CHAPTER 17 STANDBY FUNCTION
  272. Standby function control register
  273. Standby Function Operations
  274. HALT Mode Release by Interrupt Request Generation
  275. HALT Mode Release by RESET Input
  276. STOP mode
  277. STOP Mode Release by Interrupt Request Generation
  278. STOP Mode Release by RESET Input
  279. CHAPTER 18 RESET FUNCTION
  280. Timing of Reset by RESET Input
  281. Hardware Status After Reset
  282. CHAPTER 19 µ PD78P0208
  283. Internal Memory Size Switching Register
  284. Format of Internal Memory Size Switching Register (IMS)
  285. Internal Expansion RAM Size Switching Register
  286. PROM Programming
  287. PROM write procedure
  288. Page Program Mode Timing
  289. Byte Program Mode Flowchart
  290. Byte Program Mode Timing
  291. PROM read procedure
  292. Screening of One-Time PROM Version
  293. CHAPTER 20 INSTRUCTION SET
  294. Conventions
  295. Description of "operation" column
  296. Operation List
  297. Instructions Listed by Addressing Type
  298. APPENDIX A DIFFERENCES BETWEEN µ PD78044H, 780228, AND 780208 SUBSERIES
  299. APPENDIX B DEVELOPMENT TOOLS
  300. B-1 Configuration of Development Tools
  301. B.1 Software Package
  302. B.3 Control Software
  303. B.4 PROM Programming Tools
  304. B.5 Debugging Tools (Hardware)
  305. B.5.2 When using in-circuit emulator IE-78001-R-A
  306. B.6 Debugging Tools (Software)
  307. B.7 Embedded Software
  308. B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
  309. B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
  310. B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only)
  311. B.10 Notes on Target System Design
  312. B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used)
  313. APPENDIX C REGISTER INDEX
  314. C.2 Register Index (by Register Symbol)
  315. APPENDIX D REVISION HISTORY
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