NEC mPD780206 manuals
mPD780206
Table of contents
- User's Manual U11302EJ4V0UM
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- CHAPTER 1 OUTLINE
- Applications
- Pin Configuration (Top View)
- K/0 Series Lineup
- Block Diagram
- Overview of Functions
- Mask Options
- CHAPTER 2 PIN FUNCTIONS
- Description of Pin Functions
- P20 to P27 (Port
- P70 to P74 (Port
- 2.2.11 FIP0 to FIP12
- 2.2.12 V LOAD
- Pin I/O Circuits and Recommended Connection of Unused Pins
- Pin I/O Circuits
- CHAPTER 3 CPU ARCHITECTURE
- Memory Map ( µ PD780205 and µ PD780205A)
- Memory Map ( µ PD780206)
- Memory Map ( µ PD780208)
- Memory Map ( µ PD78P0208)
- Internal ROM Capacity
- Data memory addressing
- Data Memory Addressing ( µ PD780205 and µ PD780205A)
- Data Memory Addressing ( µ PD780206)
- Data Memory Addressing ( µ PD780208)
- Data Memory Addressing ( µ PD78P0208)
- Processor Registers
- Stack Pointer Format
- Data to Be Saved to Stack Memory
- General-purpose registers
- Special-function registers (SFRs)
- Special-Function Register List
- Instruction Address Addressing
- Immediate addressing
- Table indirect addressing
- Register addressing
- Operand Address Addressing
- Direct addressing
- Short direct addressing
- Special-function register (SFR) addressing
- Register indirect addressing
- Based addressing
- Based indexed addressing
- Port Functions
- Port Configuration
- Block Diagram of P00 and P04
- Port 1
- Port 2
- Block Diagram of P22 and P27
- Port 3
- Port 7
- Port 8
- Port 9
- Port 10
- Port 11
- Port 12
- Port Function Control Registers
- Format of Port Mode Register
- Format of Pull-up Resistor Option Register
- Port Function Operations
- Selection of Mask Option
- Clock Generator Functions
- Clock Generator Control Registers
- Format of Processor Clock Control Register
- Relationship Between CPU Clock and Minimum Instruction Execution Time
- Format of Display Mode Register 0
- Format of Display Mode Register 1
- System Clock Oscillator
- Subsystem clock oscillator
- Examples of Incorrect Resonator Connection
- Divider
- Clock Generator Operations
- Main system clock operations
- Subsystem clock operations
- Changing System Clock and CPU Clock Settings
- System clock and CPU clock switching procedure
- CHAPTER 6 16-BIT TIMER/EVENT COUNTER
- Bit Timer/Event Counter Functions
- Bit Timer/Event Counter Interval Time
- Bit Timer/Event Counter Configuration
- Bit Timer/Event Counter Control Registers
- Format of Timer Clock Select Register 0
- Format of 16-Bit Timer Mode Control Register
- Format of 16-Bit Timer Output Control Register
- Format of Port Mode Register 3
- Format of External Interrupt Mode Register
- Format of Sampling Clock Select Register
- Bit Timer/Event Counter Operations
- Interval Timer Operation Timing
- PWM output operations
- Pulse width measurement operations
- Configuration Diagram for Pulse Width Measurement in Free-Running Mode
- External event counter operation
- External Event Counter Configuration Diagram
- Square-wave output operation
- Bit Timer/Event Counter Operating Precautions
- Capture Register Data Retention Timing
- CHAPTER 7 8-BIT TIMER/EVENT COUNTER
- Bit Timer/Event Counter Square-Wave Output Ranges
- bit timer/event counter mode
- Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
- Format of Timer Clock Select Register 1
- Format of 8-Bit Timer Mode Control Register
- Format of 8-Bit Timer Output Control Register
- Bit Timer/Event Counter 1 Interval Time
- External Event Counter Operation Timing (with Rising Edge Specified)
- Square-Wave Output Operation Timing
- Timing After Compare Register Change During Timer Count Operation
- CHAPTER 8 WATCH TIMER
- Watch Timer Configuration
- Format of Timer Clock Select Register 2
- Format of Watch Timer Mode Control Register
- Watch Timer Operations
- CHAPTER 9 WATCHDOG TIMER
- Watchdog Timer Configuration
- Watchdog Timer Control Registers
- Format of Watchdog Timer Mode Register
- Watchdog Timer Operations
- Interval timer operation
- CHAPTER 10 CLOCK OUTPUT CONTROLLER
- Clock Output Controller Configuration
- CHAPTER 11 BUZZER OUTPUT CONTROLLER
- Buzzer Output Function Control Registers
- CHAPTER 12 A/D CONVERTER
- A/D Converter Block Diagram
- A/D Converter Control Registers
- Format of A/D Converter Mode Register
- Format of A/D Converter Input Select Register
- A/D Converter Operations
- Basic Operation of A/D Converter
- Input voltage and conversion results
- A/D converter operating mode
- A/D Conversion by Software Start
- A/D Converter Precautions
- Analog Input Pin Processing
- A/D Conversion End Interrupt Request Generation Timing
- CHAPTER 13 SERIAL INTERFACE CHANNEL 0
- Functions of Serial Interface Channel 0
- Configuration of Serial Interface Channel 0
- Control Registers of Serial Interface Channel 0
- Format of Timer Clock Select Register 3
- Format of Serial Operating Mode Register 0
- Format of Serial Bus Interface Control Register
- Format of Interrupt Timing Specification Register
- Operations of Serial Interface Channel 0
- wire serial I/O mode operation
- Wire Serial I/O Mode Timing
- RELT and CMDT Operations
- SBI mode operation
- Example of Serial Bus Configuration with SBI
- SBI Transfer Timing
- Bus Release Signal
- Address
- Commands
- Acknowledge Signal
- BUSY and READY Signals
- RELT, CMDT, RELD, and CMDD Operations (Master)
- ACKT Operation
- ACKE Operations
- ACKD Operations
- Pin Configuration
- SCK0/P27 pin output manipulation
- CHAPTER 14 SERIAL INTERFACE CHANNEL 1
- Configuration of Serial Interface Channel 1
- Control Registers of Serial Interface Channel 1
- Format of Serial Operating Mode Register 1
- Format of Automatic Data Transmit/Receive Control Register
- Format of Automatic Data Transmit/Receive Interval Specification Register
- Operations of Serial Interface Channel 1
- Circuit for Switching Transfer Bit Order
- wire serial I/O mode operation with automatic transmit/receive function
- Basic Transmission/Reception Mode Operation Timing
- Basic Transmission/Reception Mode Flowchart
- Basic Transmission Mode Operation Timing
- Basic Transmission Mode Flowchart
- Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode)
- Repeat Transmission Mode Operation Timing
- Repeat Transmission Mode Flowchart
- Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)
- Automatic Transmission/Reception Suspension and Restart
- System Configuration with Busy Control Option
- Operation Timing When Using Busy Control Option (BUSY0 = 0)
- Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
- Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1)
- Automatic Transmit/Receive Interval
- Interval Determined by CPU Processing (with Internal Clock Operation)
- Interval Determined by CPU Processing (with External Clock Operation)
- CHAPTER 15 VFD CONTROLLER/DRIVER
- VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0)
- VFD Controller/Driver Configuration
- VFD Controller/Driver Control Registers
- Format of Display Mode Register 2
- One-display period and cut width
- Selecting Display Mode
- Display Mode and Display Output
- Display Data Memory
- Key Scan Flag and Key Scan Data
- Light Leakage of VFD
- Display Examples
- Segment type (display mode 1: DSPM05 = 0)
- Dot type (display mode 1: DSPM05 = 0)
- Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode
- Display Data Memory Configuration and Data Reading Order (Display Mode 2)
- Grid Driving Timing
- Calculating Total Power Dissipation
- Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode
- CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
- Interrupt Sources and Configuration
- Basic Configuration of Interrupt Function
- Interrupt Function Control Registers
- Format of Interrupt Request Flag Register
- Format of Interrupt Mask Flag Register
- Format of Priority Specification Flag Register
- Noise Eliminator I/O Timing (When Rising Edge Is Detected)
- Format of Program Status Word
- Interrupt Servicing Operations
- Non-Maskable Interrupt Request Acknowledgment Flowchart
- Non-Maskable Interrupt Request Acknowledgment Operation
- Maskable interrupt request acknowledgment operation
- Interrupt Request Acknowledge Processing Algorithm
- Software interrupt request acknowledgment operation
- Multiple interrupt servicing
- Multiple Interrupt Servicing Example
- Interrupt request hold
- Test Functions
- Test input signal acknowledgment operation
- CHAPTER 17 STANDBY FUNCTION
- Standby function control register
- Standby Function Operations
- HALT Mode Release by Interrupt Request Generation
- HALT Mode Release by RESET Input
- STOP mode
- STOP Mode Release by Interrupt Request Generation
- STOP Mode Release by RESET Input
- CHAPTER 18 RESET FUNCTION
- Timing of Reset by RESET Input
- Hardware Status After Reset
- CHAPTER 19 µ PD78P0208
- Internal Memory Size Switching Register
- Format of Internal Memory Size Switching Register (IMS)
- Internal Expansion RAM Size Switching Register
- PROM Programming
- PROM write procedure
- Page Program Mode Timing
- Byte Program Mode Flowchart
- Byte Program Mode Timing
- PROM read procedure
- Screening of One-Time PROM Version
- CHAPTER 20 INSTRUCTION SET
- Conventions
- Description of "operation" column
- Operation List
- Instructions Listed by Addressing Type
- APPENDIX A DIFFERENCES BETWEEN µ PD78044H, 780228, AND 780208 SUBSERIES
- APPENDIX B DEVELOPMENT TOOLS
- B-1 Configuration of Development Tools
- B.1 Software Package
- B.3 Control Software
- B.4 PROM Programming Tools
- B.5 Debugging Tools (Hardware)
- B.5.2 When using in-circuit emulator IE-78001-R-A
- B.6 Debugging Tools (Software)
- B.7 Embedded Software
- B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
- B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
- B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only)
- B.10 Notes on Target System Design
- B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used)
- APPENDIX C REGISTER INDEX
- C.2 Register Index (by Register Symbol)
- APPENDIX D REVISION HISTORY
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