IBM Power Systems 775 Manual

Contents

Chapter 1. Understanding the IBM Power Systems 775 Cluster 5Figure 1-1 POWER7 chip block diagramIBM POWER7 characteristicsThis section provides a description of the following characteristics of the IBM POWER7 chip,as shown in Figure 1-1: 240 GFLOPs:– Up to eight cores per chip– Four Floating Point Units (FPU) per core– Two FLOPS/Cycle (Fused Operation)– 246 GFLOPs = 8 cores x 3.84 GHz x 4 FPU x 2) 32 KBs instruction and 32 KBs data caches per core 256 KB L2 cache per core 4 MB L3 cache per core Eight Channels of SuperNova buffered DIMMs:– Two memory controllers per chip– Four memory busses per memory controller (1 B wide Write, 2 B wide Read each) CMOS 12S SOI 11 level metal Die size: 567 mm2Memory Controller1B Write2B Read1B Write2B Read1B Write2B Read1B Write2B ReadMemory Controller1B Write2B Read1B Write2B Read1B Write2B Read1B Write2B ReadCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBCore4 FXU, 4 FPU4T SMTL2256KBL34MBFabricp78B X-Bus8B X-BusQCMChip ConnectionsAddess/Data8B Y-Bus8B Y-BusQCMChip ConnectionsAddress/Data8B Z-Bus8B Z-BusQCMChip ConnectionsAddress/Data8B A-Bus8B A-BusQCMChip ConnectionsData8B B-Bus8B B-BusQCMChip ConnectionsData8B C-Bus8B C-BusQCMChip ConnectionsDataQCM to HubConnectionsAddress/DataPSII2C On Module SEEPRMI2C On Module SEEPRM1.333Gb/sBuffered DRAM1.333Gb/sBuffered DRAM1.333Gb/sBuffered DRAM1.333Gb/sBuffered DRAMFSI FSP1 - BFSI FSP1 - AOSC OSC - BOSC OSC - ATPMD TPMD-A, TPMD-B8B W/Gx-Bus8B W/Gx-BusTOD SyncFSIDIMM_1FSIDIMM_2FSIDIMM_3FSIDIMM_4FSIDIMM_1FSIDIMM_2FSIDIMM_3FSIDIMM_4.