Kenwood TK-5210G Service Manual

Also see for TK-5210: Specifications Instruction manual Specifications Instruction manual Service manual

TK-5210 (G)22Q307Ripple filter5CIC414RheostatQ310,Q311VCOIC303PLL ICPLDAFCPCS_RFSDO0SCK0D101SWIC3041/2IC502DACX301VCXOIC10ASICto pre-pre-drive(Q101)Q315Ripple filter15VD210SWto 1st mixer(IC202)PCS_potSDO0SCK0Q308,Q309IC301ASSISTQ312Q306BUFFBUFFIC500 VCO_MODTCXO_ MODSUMQ314BUFFVCOSW1LPFCVCIRCUIT DESCRIPTION5-3. Rheostat (IC414)The rheostat (IC414) is connected to the VCO voltagecontrol terminal, “V-assist”, and quickly controls the VCOoscillation frequency. However, its accuracy is low and theVCO frequency cannot be matched accurately with thedesired transmit carrier or the 1st local receive signal. Therheostat is controlled by the ASIC (IC10) through the 3-lines“PCS_pot”, “SDO0”, “SCK0” serial bus.5-4. PLL IC (IC303)PLL IC compares the differences in phases of the VCOoscillation frequency and the VCXO reference frequency,returns the difference to the VCO CV terminal and realizesthe “Phase Locked Loop” for the return control. This allowsthe VCO oscillation frequency to accurately match (lock) thedesired frequency.When the frequency is controlled by the PLL, the fre-quency convergence time increases as the frequency dif-ference increases when the set frequency is changed. Tosupplement this, the ASIC (IC10) is used before control bythe PLL IC to bring the VCO oscillation frequency close tothe desired frequency. As a result, the VCO CV voltage doesnot change and is always stable at approx. 2.0V.The desired frequency is set for the PLL IC by the ASICthrough the 3-line “PCS_RF”, “SDO0”, “SCK0” serial bus.Whether the PLL IC is locked or not is monitored by theASIC through the “PLD” signal line. If the VCO is not thedesired frequency (unlock), the “PLD” logic is low.5-5. Local Switch (D101, D210)The connection destination of the signal output from the1/2 driver (IC304) is changed with the diode switch (D101)that is controlled by the transmission power supply, 5T, andthe diode switch (D210) that is controlled by the receivepower supply, 5R.If the 5T logic is high, it is connected to a send-side pre-pre-drive (Q101). If the 5T logic is low, it is connected to areceive-side mixer (IC202).Fig. 8 PLL block diagram6. Control CircuitThe control circuit consists of the ASIC (IC10) and its pe-ripheral circuits. IC10 mainly performs the following;1) Switching between transmission and reception by PTTsignal input.2) Reading system, zone, frequency, and program datafrom the memory circuit.3) Sending frequency program data to the PLL.4) Controlling squelch on/off by the DC voltage from thesquelch circuit.5) Controlling the audio mute circuit by decode data input.6-1. ASICThe ASIC (IC10) is 32bit RISC processor, equipped withperipheral function and ADC/DAC.This CPU operates at 18.432MHz clock and 3.3V/1.5VDC. It controls the flash memory, SRAM, DSP, the receivecircuit, the transmitter circuit, the control circuit, and the dis-play circuit and transfers data to or from an external device.