CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)User’s Manual U16896EJ2V0UD 42514.6.2 Serial clock generationA serial clock can be generated according to the settings of the CKSRn and BRGCn registers.The base clock to the 8-bit counter is selected by the CKSRn.TPSn3 to CKSRn.TPSn0 bits.The 8-bit counter divisor value can be set by the BRGCn.MDLn7 to BRGCn.MDLn0 bits.(1) Clock select register n (CKSRn)The CKSRn register is an 8-bit register for selecting the base clock using the TPSn3 to TPSn0 bits. Theclock selected by the TPSn3 to TPSn0 bits becomes the base clock (f UCLK ) of the transmission/receptionmodule.This register can be read or written in 8-bit units.Reset sets this register to 00H.Caution Clear the ASIMn.UARTEn bit to 0 before rewriting the TPSn3 to TPSn0 bits.70CKSRn(n = 0, 1)6050403TPSn32TPSn21TPSn10TPSn0After reset: 00H R/W Address: CKSR0 FFFFFA06H, CKSR1 FFFFFA16HTPSn3 TPSn2 TPSn1 TPSn0 Base clock (f UCLK )Note 10 0 0 0 f XX0 0 0 1 f XX/20 0 1 0 f XX/40 0 1 1 f XX/80 1 0 0 f XX/160 1 0 1 f XX/320 1 1 0 f XX/640 1 1 1 f XX/1281 0 0 0 f XX/2561 0 0 1 f XX/5121 0 1 0 f XX/1,0241 0 1 1 External clockNote 2 (ASCK0 pin)Other than above Setting prohibitedNotes 1. Set f UCLK so as to satisfy the following conditions.• V DD = 4.5 to 5.5 V: f UCLK ≤ 12 MHz• V DD = 2.7 to 4.5 V: f UCLK ≤ 6 MHz2. ASCK0 pin input clock can be used only by UART0.Setting of UART1 is prohibited.Remark f XX: Main clock frequency
