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NEC V850ES/KE1+ User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. CHAPTER 1 INTRODUCTION
  11. K0/Kx1+, 78K0/Kx1 products lineup
  12. Features
  13. Applications
  14. Pin Configuration (Top View)
  15. Function Block Configuration
  16. Overview of Functions
  17. CHAPTER 2 PIN FUNCTIONS
  18. Pin I/O Circuits and Recommended Connection of Unused Pins
  19. Pin I/O Circuits
  20. CHAPTER 3 CPU FUNCTIONS
  21. CPU Register Set
  22. Program register set
  23. System register set
  24. Operating Modes
  25. Address Space
  26. Wraparound of CPU address space
  27. Memory map
  28. Areas
  29. Recommended use of address space
  30. Peripheral I/O registers
  31. Special registers
  32. Cautions
  33. CHAPTER 4 PORT FUNCTIONS
  34. Port Configuration
  35. Port 0
  36. Port 3
  37. Port 4
  38. Port 5
  39. Port 7
  40. Port 9
  41. Port CM
  42. Port DL
  43. Block Diagrams
  44. Port Register Setting When Alternate Function Is Used
  46. Hysteresis characteristics
  47. CHAPTER 5 CLOCK GENERATION FUNCTION
  48. Configuration
  49. Registers
  50. Operation
  51. PLL Function
  52. Usage
  53. CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
  57. Timer output operations
  58. Eliminating Noise on Capture Trigger Input Pin (TIP0a)
  60. CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
  64. Square wave output operation
  65. External event counter operation
  66. Operation in clear & start mode entered by TI010 pin valid edge input
  67. Free-running timer operation
  68. PPG output operation
  69. One-shot pulse output operation
  70. Pulse width measurement operation
  71. Special Use of TM01
  73. CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5
  77. Operation as external event counter
  78. Square-wave output operation
  79. bit PWM output operation
  80. Operation as interval timer (16 bits)
  81. Operation as external event counter (16 bits)
  82. Square-wave output operation (16-bit resolution)
  84. CHAPTER 9 8-BIT TIMER H
  87. PWM output mode operation
  88. Carrier generator mode operation
  89. CHAPTER 10 INTERVAL TIMER, WATCH TIMER
  92. Watch Timer
  93. Register
  96. CHAPTER 11 WATCHDOG TIMER FUNCTIONS
  99. Watchdog Timer 2
  102. Function
  107. Security Function
  108. Overview
  112. Trigger modes
  113. Operation modes
  114. Power fail detection function
  115. Setting method
  117. How to Read A/D Converter Characteristics Table
  121. Interrupt Request Signals
  123. Transmit operation
  124. Continuous transmission operation
  125. Receive operation
  126. Reception error
  127. Parity types and corresponding operation
  128. Receive data noise filter
  129. SBF transmission/reception (UART0 only)
  130. Dedicated Baud Rate Generator n (BRGn)
  131. Serial clock generation
  132. Baud rate setting example
  133. Allowable baud rate range during reception
  134. Transfer rate during continuous transmission
  135. CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0)
  139. Single transfer mode
  140. Continuous transfer mode
  141. Output Pins
  145. Functions
  146. Start condition
  147. Addresses
  148. Stop condition
  149. Wait state
  150. Master device operation
  151. Slave device operation (when receiving slave address (match with address))
  152. Slave device operation (when receiving extension code)
  153. Operation without communication
  154. Operation when arbitration loss occurs (no communication after arbitration loss)
  155. Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control
  156. Address Match Detection Method
  157. Extension Code
  158. Arbitration
  159. Wakeup Function
  160. Communication Reservation
  161. When communication reservation function is disabled (IICF0.IICRSV0 bit
  163. Communication Operations
  164. Master operation in single master system
  165. Master operation in multimaster system
  166. Slave operation
  167. Timing of Data Communication
  168. CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
  169. Non-Maskable Interrupts
  171. Restore
  172. NP flag
  173. Maskable Interrupts
  175. Priorities of maskable interrupts
  176. Interrupt control register (xxlCn)
  177. Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3)
  178. In-service priority register (ISPR)
  179. ID flag
  180. Watchdog timer mode register 1 (WDTM1)
  181. External Interrupt Request Input Pins (NMI, INTP0 to INTP7)
  182. Edge detection
  183. Software Exceptions
  185. EP flag
  186. Exception Trap
  187. Debug trap
  188. Multiple Interrupt Servicing Control
  189. Interrupt Response Time
  190. Periods in Which Interrupts Are Not Acknowledged by CPU
  191. CHAPTER 18 KEY INTERRUPT FUNCTION
  193. CHAPTER 19 STANDBY FUNCTION
  195. HALT Mode
  196. IDLE Mode
  197. STOP Mode
  198. Securing oscillation stabilization time when STOP mode is released
  199. Subclock Operation Mode
  200. Sub-IDLE Mode
  201. CHAPTER 20 RESET FUNCTION
  202. Register to Check Reset Source
  203. Reset Sources
  204. Reset operation by WDTRES1 signal
  205. Reset operation by WDTRES2 signal
  206. Power-on-clear reset operation
  207. Reset operation by low-voltage detector
  208. Reset operation by clock monitor
  209. Reset Output Function
  210. CHAPTER 21 CLOCK MONITOR
  212. Internal Oscillation Clock Operation Mode
  213. Internal Oscillation HALT Mode
  214. CHAPTER 22 LOW-VOLTAGE DETECTOR
  217. CHAPTER 23 POWER-ON-CLEAR CIRCUIT
  219. CHAPTER 24 ROM CORRECTION FUNCTION
  220. Control Registers
  221. Correction control register (CORCN)
  222. CHAPTER 25 MASK OPTION/OPTION BYTE
  223. Option Byte (Flash Memory Versions)
  224. CHAPTER 26 FLASH MEMORY
  225. Memory Configuration
  226. Functional Outline
  227. Rewriting by Dedicated Flash Programmer
  228. Communication mode
  229. Flash memory control
  230. Selection of communication mode
  231. Communication commands
  232. Pin connection
  233. Rewriting by Self Programming
  235. Standard self programming flow
  236. Flash functions
  237. Internal resources used
  238. ROM Security Function
  239. Setting
  241. CHAPTER 28 ELECTRICAL SPECIFICATIONS
  242. CHAPTER 29 PACKAGE DRAWINGS
  243. APPENDIX A DEVELOPMENT TOOLS
  244. A.1 Software Package
  245. A.4 Debugging Tools (Hardware)
  246. A.5 Debugging Tools (Software)
  247. A.6 Embedded Software
  248. APPENDIX B INSTRUCTION SET LIST
  249. B.2 Instruction Set (in Alphabetical Order)
  250. APPENDIX C REGISTER INDEX
  251. D.1 Major Revisions in This Edition
NEC V850ES/KE1+ User Manual Manual pdf 676 page image
User’s Manual U16896EJ2V0UD676CHAPTER 29 PACKAGE DRAWINGS483233641171649SS64-PIN PLASTIC TQFP (12x12)ITEM MILLIMETERSG 1.125A 14.0±0.2C 12.0±0.2DF 1.12514.0±0.2B 12.0±0.2N 0.10PQ 0.1±0.051.0SR 3°+4°−3°RHKJQGISPdetail of lead endNOTEEach lead centerline is located within 0.13 mm ofits true position (T.P.) at maximum material condition.MH 0.32+0.06−0.10I 0.13JK 1.0±0.20.65 (T.P.)L 0.5M 0.17 +0.03−0.07P64GK-65-9ET-3TU 0.6±0.150.25FMABC DNTLU1.1±0.1
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This manual is suitable for:
?PD703302?PD703302Y?PD70F3302?PD70F3302YmPD703207mPD703207YmPD70F3207HmPD70F3207HYV850ES/KE1V850ES/KE1+
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