CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTIONUser’s Manual U16896EJ2V0UD54217.3.2 RestoreExecution is restored from maskable interrupt servicing by the RETI instruction.When the RETI instruction is executed, the CPU performs the following processing and transfers control to theaddress of the restored PC.(1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit and thePSW.NP bit are both 0.(2) Transfers control to the loaded address of the restored PC and PSW.Figure 17-5 shows the processing flow of the RETI instruction.Figure 17-5. RETI Instruction ProcessingRETI instructionOriginal processing restoredPCPSWISPR.corresponding-bitNoteEIPCEIPSW0PSW. EP1010PCPSWFEPCFEPSWPSW. NPNote For the ISPR register, refer to 17.3.6 In-service priority register (ISPR).Caution When the EP bit and the NP bit are changed by the LDSR instruction during maskableinterrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETIinstruction, it is necessary to clear the EP bit back to 0 and the NP bit back to 0 using theLDSR instruction immediately before the RETI instruction.Remark The solid line shows the CPU processing flow.
