Philips BJ2.4U Service Manual

Circuit Descriptions, Abbreviation List, and IC Data SheetsEN 134 BJ2.4U/BJ2.5U PA9.DCU (Data Capturing Unit)Figure 9-21 DCU block diagramThe purpose of this block is to acquire digital data (containingTeletext, Closed Captions, ...) from a CVBS/Y/C video inputsource. It performs processing on the received data andprovides the data to the ITU-656 formatter unit.The decimator reduces the sample rate (from 27 MHz to 13.5MHz) of the incoming digitized CVBS or Y data stream from theI 2 D receiver. From the video input, the data slicer reconstructsthe transmitted bit stream and associated clock. The SERPARblock converts the serial bits, coming from the data slicer, intoparallel bytes. The packet processor performs data decodingand some error correction, assembles received bytes intopacket structure, and streams out the data to the ITU-656formatter.The acquisition-timing block locks onto sync signals, andprovides timing information to the other blocks of the datacapture unit.ITU656 Output FormatterFigure 9-22 ITU656 formatter block diagramThe ITU656 formatter gets YUV data as video input signal,coming from the VIDDEC block. These YUV data are eitherdecoded CVBS signals, matrixed RGB signals, or YUV inputsignals. The second input data are VBI sliced data coming fromthe DCU. The output of the ITU delivers a data stream, whichis ITU-601/656/1364 compliant, and includes video as well asthe VBI data.DEMDEC (Demodulator and Decoder)Figure 9-23 DEMDEC block diagramThe demodulator and decoder (DEMDEC) is responsible fordemodulating and decoding incoming SIF signals.The main features of the DEMDEC are:• Auto Standard Detection (ASD).• DQPSK demodulation for different standards,simultaneously with 1-channel demodulation.• NICAM decoding (B/G, I, D/K, and L standard).• Two-carrier multi standard FM demod. (B/G, D/K and M).• Optional AM demodulation for system L, simultaneouslywith NICAM.• Identification A2 systems (B/G, D/K and M standard) withdifferent identification time constants.• FM pilot carrier present detector.• BTSC MPX decoder.• SAP decoder.• dBx noise reduction.• Japan (EIAJ) decoder.• FM radio decoder.Audio ProcessingFigure 9-24 Audio processing block diagramMain features are:• Master volume control and Balance.• Tone control (Loudness, Bass, Treble, Equalizer).• Dolby ProLogic delay.• Incredible Mono and Stereo.• Virtual Dolby Surround (VDS 522, 523).• Virtual Dolby Digital (VDD 522, 523).• Digital audio I/O interface (stereo I2S input interface).• Eight audio DACs for six channel loudspeaker outputs andstereo headphones output.• Audio DACs for stereo SCART output and stereo LINEoutput.• Serial data link interface for interfacing with the analogmulti-purpose interface IC PNX3000 (MPIF).E_14700_072.eps310505Data Capture UnitData SlicerDecimatorAcquisitionTimingSERPAR PacketFormatterVBI datapacketsI2d Data_1(cvbs)I2d Data_2(Y)H/V SyncField IdE_14700_073.eps310505ITU656 FormatterVideo DataProcessingVBI DataProcessingSERPARITU_out (9:0)YUVVBI datapacketsITU_ClkITU_DATA_VALIDE_14700_074.eps300505downmixerdecimationFM / AMdemod.ch. 1FM / AMdemod.ch. 2NICAMdemod. &decoderFM identMPXdemod.SAP / EIAJdemod.noisedetectorhardwarecontrol &status reg.pre-processdecimationfilters,deemph.,dbx,selectSRC5 channelstceles&xirtamedDDEP (DemDec Easy Programming)decimation224ADC1,2, PIPMONO, Ext. AMDEMDEC DSPDEC L/ADEC R/BMONOSAPPIPMONOADCSIFcontrol / status registers (XMEM)2f 1 f 2f pilotfs = 27 MHz+L, RSUBCMaster Volume & TrimOFF/ I-Mono /I-StereoMAINBa/Tror EQLoudn.orBBE®Bass ManagementDelayDigital Output CrossbarCBa/Tror EQLoudn.Ls/RsBa/Tror EQL,RSMAUX1Ba/TrAUX1Vol/TrimAUX1SMAUXxVol/TrimAUXxSMNoise/SilenceGen.(L+R)/2SUBSMCSMLsSM+DAFO1I2S1L,R OUTtoI2S6L,R OUTMAINCLsAUX1/ HPAUX2,3,4,5,65 equal channels for I2S, DAC1, DAC2C INS/Ls INL,RAudio MonitorLevel Adj.AUX2-6Digital Input Crossbar ( SSel, Matrix )AUX1 MAINRs INL,RLFERsLsRsLsRs RsSM+ SW FilterBeeper6DAFO2DAFO3DAFO4DAFO5DAFO6DAFO7DAFO8DPL II ®DUB or DBEin L,R or SUBHall/MatrixL,R,C,Ls,Rs (DPL II)5Automatic Volume LevelingCS/LsRsLFEAVLContr.Acoustical CompensationDEC (L/A,R/B, Mono, SAP)PIPMONOADC (L/A, R/B)I2S IN 1 to 6LevelAdj.VIRTVDS ®522,523VDD ®522,523MAIN MSelCMSelS,LsRsMSelL,R (DPL II)L,R (M,ST, 5.1)L,R (M,ST, 5.1)C (DPL II)C INC Hall/Matrix(L+R)/2C VIRTL,R VIRTLs,Rs (DPL II)S/Ls INS Hall (L+R)/2S Matrix (L-R)/2Rs INDAC2L,RDAC1L,RE_14700_075.eps250505