Philips BJ2.4U Service Manual

Circuit Descriptions, Abbreviation List, and IC Data SheetsEN 136 BJ2.4U/BJ2.5U PA9.Figure 9-26 LVDS technologyThe digital video output from the VIPER is connected to thedisplay via the LVDS interface. This transmitter converts 28 bitsof LVCMOS/LVTTL data into four LVDS (Low VoltageDifferential Signalling) data streams. A phase-locked transmitclock is transmitted in parallel with the data streams over a fifthLVDS link. With every cycle of the transmit clock, 28 bits ofinput data are sampled and transmitted. At a transmit clockfrequency of 85 MHz, 24 bits of RGB data and 3 bits of LCDtiming and control data (FPLINE, FPFRAME, DRDY) aretransmitted at a rate of 595 Mbps per LVDS data channel.Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec.9.12 PNX2015: Stand-by Processor9.12.1 IntroductionThe Stand-by Processor’s sub system is isolated from the othersub systems within thePNX2015. It has its own power supply(1.2V and 3.3V), together with separate clocking (16MHz) andreset. This allows for it to be active while all other sub systemsare either inactive, via clock being disabled, or powered down.The main tasks of the Stand-by Controller are:• RC5/RC6 remote control handling.• P50.• Keyboard handling (side control, “on/off” switch).• Detection and protection of the power supplies.• Status detection on EXTernals.• SAM/SDM entering.• Provide boot-scripts to the VIPER.• Start-up behavior of the set; sequentially enabling thepower supplies via the ENABLE lines.9.12.2 TV Start-up Behavior and Fault Detection1. The Stand-by Controller is powered by the +5V2 voltage(3V3_STBY voltage is derived from the +5V2), whichbecomes available when the set is connected to the Mains/ AC Power.2. By default, all I/O lines of the controller are “high”, this stateis also the state that will not trigger protections or causesupplies to rise, since enabling a supply requires that an IOline is pulled "low". Also all protections are active "low".3. The 16 MHz crystal starts running.4. Reset IC 7M03 will generate a RESET_STBY pulse.5. All I/O lines will be set in default state, as “told” by thesoftware.– RESET_SYSTEM will be "low" (this will hold theVIPER in reset).– LAMP_ON will be "low".6. The system waits for an RC or functional switch command:when this command is "low" the set will start-up.The Stand-by Microprocessor is responsible for the start-up ofthe VIPER, by providing the correct timing for the DC/DCconverted voltages (for timing of DC/DC converter voltages seedescription in paragraph "Power Supply").The +12V switch (via POD_MODE) and the DC/DC converters(via ENABLE) are switched "on" (active "low"). Once thesevoltages are switched "on", the Stand-by Controller ismonitoring these voltages via a voltage detector circuitconnected to port P2.x. When one of the voltages is missing,the fault detection will be active "low" on port P2.x. An errorcode will be written in the error buffer.There is a common SUPPLY_FAULT line; connected to portP1.3 (INT5) that is active "low" when there is a problemdetected on one of the DC/DC power supplies driver circuits.One input (P2.6) is used for the Audio Supply protection fromthe audio amplifier.The RESET_SYSTEM line (P4.0) is "low" in Stand-by and atStart-up to keep the VIPER in reset state. Once the VIPER coresupply is available, the RESET_SYSTEM line will become"high". The VIPER is starting up and will provide a RESET-MIPS active "high" to the Stand-by Processor P3.3, AVIP, andCOLUMBUS.9.12.3 I/O Stand-by ProcessorThe inputs on the Stand-by Microprocessor are used to detectthe AV status from the front inputs (see also the control blockdiagram in chapter 6 "Block diagrams,...").An UART communication line via an electronic switch isavailable on a connector and will be used for Service tocommunicate with ComPair. The UART line is switched to theStand-by Processor when the UART_SWITCH line (P0.7) is"high". Otherwise it is switched to the VIPER.9.13 VIPER 2 (PNX 8550)9.13.1 IntroductionThe PNX8550 is a highly integrated media processor intendedfor deployment in analog, digital, and hybrid TV receivers. Itcan be used for 100 Hz interlaced as well as 60 Hz progressivescreens. It is fully capable of performing advanced videoimprovement algorithms, such as Digital Natural Motion™, onStandard Definition analog or digital sources. It includes an HDcapable de-interlacer for converting interlaced HDtransmission signals to progressive output for driving wide-XGA class Plasma or LCD displays. Two 32-bit 240 MHz VLIWmedia processors, referred to as the TriMedia TM3260 CPUcore, carry out the advanced video improvement processing aswell as all audio operations. Fixed hardware functions performstable core video functions, such as picture level MPEG2decoding, scaling, image composition and pixel postprocessing.The PNX8550 provides a primary digital (YUV or RGB) outputto connect to the display specific output processor. In addition,a secondary analog video output (CVBS or S-Video) for a VCRis available. This is the so-called DENC-out. It can operateeither in analog PAL/NTSC or digital mode.CL 36532053_073.eps3107031 0 1 0Standard Single Ended Single Signal & LargerVoltage swingLow Voltage Differential SignallingTwo Signals & Smaller Voltage SwingNoise- Lower Voltage Swing (only 350 mV vs. 3 V)- Standard open Ended: 250Mbps- LVDS: >1 Gbps- Allows faster Clocking- Differential Signals (Two Signals) ...Low Noise!- Receiver reads a 1 or 0 based on the delta of the two signals.- Noise Impacts both lines and cancels out each others.1 0 1 0