Philips BJ2.4U Service Manual

Circuit Descriptions, Abbreviation List, and IC Data Sheets EN 135BJ2.4U/BJ2.5U PA 9.9.9 PNX2015: Columbus (Comb Filter)9.9.1 IntroductionThis block provides the following picture improvementfunctions:• Enhanced 2D combing for PAL and NTSC.• 3D field combing for PAL and NTSC.• 3D frame combing for PAL and NTSC.• Spatial noise reduction for all component video standards.• Temporal noise reduction for all component videostandards.The comb filter is controlled via a separate I 2 C interface on thePNX2015, this is to ensure registers containing measurementinformation, are accessed at appropriate times. Themeasurement information is also available as ancillary datawithin the video stream (ITU-656).For certain features of the comb filter, access to externalmemory is required. The PNX2015 has a unified memory thatboth comb filter and HD subsystem’s share concurrently.9.9.2 Block DiagramFigure 9-25 COLUMBUS internal block diagramFigure above, shows a block diagram of the Columbus combfilter in the PNX2015 device. An input video signal is suppliedby the AVIP and fed to the Columbus block. The signal issupplied in digitized components of:• CVBS or Y.• Uncombed U.• Uncombed V.The CVBS signal is combed, extracting the luminancecomponents and rejecting the chroma components. The UVsignals are combed, rejecting the left over luminancecomponents, from a previous filtering (normally band passfiltered).The outputs from the 3D comb filter are:• Combed luminance signal (Y).• Combed U signal.• Combed V signal.The output from the 3D comb filter feeds the SWAN and LOREnoise reduction block, which performs spatial/temporal noisereduction, for both luminance and chrominance components.Control Register InterfaceThe control registers are accessed via I 2C. Most signals thatcan be written via I 2 C are double buffered. The fast I 2 Cinterface implemented on the COLUMBUS is a 5V compliant,400 kHz slave receiver/transmitter. The I2 C will not be blockedduring voltage shorts or opens.For the system dependent parameters of the 3D-Comb filter,five register banks are present. Data can be written in one ofthe banks via I 2 C, by programming bits [2:0] of theSYSTEM_SELECT register. The bits [6:4] of theSYSTEM_SELECT register select, which register bank is usedby Columbus to define the filter settings.Internal Test GeneratorsThere are two test generators inside the COLUMBUS chip:• The "656 test generator" generates a 656 compliant streamand is used for testing the functionality of the 656 encoderand decoder. The 656 stream can be injected at the frontend or the back end of the chip.• A second internal test pattern generator enables testing ofthe device and attached external memory (if present). Thetest pattern generator signal can be inserted at the frontend of the chip (passing through the 3D Comb and noisereduction system and external memory) or at the back endof the chip. Test patterns are available for both PAL/SECAM and NTSC systems.9.10 PNX2015: HD SubsystemThe HD subsystem performs MPEG video decoding on HD/SDtransport streams. It interfaces with the PNX8550 and videocoprocessor via tunnel interfaces, HD/SD using DV4 and DV5inputs, and PNX8550 using DV1, DV2 and DV3 outputs. TheHD subsystem can also perform horizontal and vertical scalingof video images, and perform a range of video measurementson a transport stream.9.11 PNX2015: LVDS TransmitterLow Voltage Differential Signaling (LVDS) is a low-power, low-noise differential technology for high speed data transmissionover two PWB traces, or a balanced cable. LVDS allows single-channel data transmission at hundreds, or even up to athousand Mbps. Low swing and current-mode driver outputscreate low noise and provide very low power consumptionacross frequency ranges.The LVDS transmitter IP provides a connection interface toFPDs.Differences between standard and LVDS signalling:• Standard single ended signal (TTL):– Requires 28 signal lines and more than 14 grounds.– Single ended signals up to 3 V.– Wide flat ribbon cable.– EMI/EMC problems.– Feasible up to VGA/NTSC resolution (limited to 250Mb/s).• LVDS:– Five low voltage (350 mV) differential pairs: one clockpair and four data pairs.– Five grounds.– EMI/EMC friendly.– WXGA and HD-1280x720p (up to 1 Gb/s).LVDS offers superior performance compared to the standardsingle ended signal (TTL).It is even "protocol independent" so it requires no software.Memory Interface3D CombPAL & NTSCLocal Regression&SWAN 3DNoise Reduction656 Decoder656 EncoderPatternTestGeneratorY/CVBSUVUV (ITU656)Y (ITU656)NoiseMeasurementSEL656Mux MuxMuxSEL656WEB/DAVBWEA/DAVADQ(16:1)A(11:0)CONTROL656TestGeneratorE_14700_083.eps300505Bank number System0 PAL B, G, H, I, D, K1 PAL M2 PAL N3 NTSC4 Bypass