126 www.xilinx.com RocketIO™ X Transceiver User Guide1-800-255-7778 UG035 (v1.5) November 22, 2004Chapter 5: Simulation and ImplementationRMGT Package PinsThe MGTs make up a hard core placed in the FPGA fabric; all package pins for the MGTsare dedicated on the Virtex-II Pro X device. This is shown in the package pin diagrams inthe Virtex-II Pro data sheet. When creating a design, LOC constraints must be used toimplement a specific MGT on the die. This LOC constraint also determines which packagepins are used. Table 5-1 and Table 5-2 show the correlation between the LOC grid and thepackage pins themselves. The pin numbers are the TXNPAD, TXPPAD, RXPPAD, andRXNPAD, respectively. The power pins are adjacent to these pins in the package pindiagrams of the handbook.Table 5-1: LOC Grid and Package Pins Correlation for FF896PackageLOC Constraints FF896XC2VPX20GT_X0_Y0 AK27, AK26, AK25, AK24GT_X0_Y1 A27, A26, A25, A24GT_X1_Y0 AK20, AK19, AK18, AK17GT_X1_Y1 A20, A19, A18, A17GT_X2_Y0 AK14, AK13, AK12, AK11GT_X2_Y1 A14, A13, A12, A11GT_X3_Y0 AK7, AK6, AK5, AK4GT_X3_Y1 A7, A6, A5, A4Table 5-2: LOC Grid and Package Pins Correlation for FF1704 PackagesLOC Constraints FF1704XC2VPX70GT_X0_Y0 BB41, BB40, BB39, BB38GT_X0_Y1 A41, A40, A39, A38GT_X1_Y0 BB37, BB36, BB35, BB34GT_X1_Y1 A37, A36, A35, A34GT_X2_Y0 BB33, BB32, BB31, BB30GT_X2_Y1 A33, A32, A31, A30GT_X3_Y0 BB29, BB28, BB27, BB26GT_X3_Y1 A29, A28, A27, A26GT_X4_Y0 BB25, BB24, BB23, BB22GT_X4_Y1 A25, A24, A23, A22GT_X5_Y0 BB21, BB20, BB19, BB18GT_X5_Y1 A21, A20, A19, A18
