Xilinx RocketIO X User Manual

Also see for RocketIO: User guide User guide User guide

Contents

Xilinx RocketIO X User Manual Manual pdf 63 page image

RocketIO™ X Transceiver User Guide www.xilinx.com 63UG035 (v1.5) November 22, 2004 1-800-255-7778Block Level Functions RThe state machine works by keeping track of valid and invalid sync headers. Upon reset,block lock is deasserted, and the state is LOCK_INIT. The next state is RESET_CNT whereall counters are zeroed out. When test_sh is asserted, the next state is TEST_SH, whichchecks the validity of the sync header. If it is valid, the next state is VALID_SH, if not, thestate changes to INVALID_SH.From VALID_SH, if sh_cnt is less than the attribute value sh_cnt_max and test_sh isHigh, the next state is TEST_SH. If sh_cnt is equal to sh_cnt_max andsh_invalid_cnt equals 0, the next state is GOOD_64 and from there block_lock isasserted. Then the process repeats again and the counters are zeroed.If at TEST_SH sh_cnt equals sh_cnt_max, but sh_invalid_cnt is greater than zero,then the next state is RESET_CNT. From INVALID_SH, if sh_invalid_cnt equalssh_invalid_cnt_max, or if block_lock is not asserted, the next state is SLIP, wherebit_slip is asserted, and then on to RESET_CNT. If sh_cnt equals sh_cnt_max andsh_invalid_cnt is less than sh_invalid_cnt_max and block_lock is asserted, thengo back to RESET_CNT without changing block_lock or bit_slip.Finally, if test_sh is High and sh_cnt is less than sh_cnt_max, andsh_invalid_cnt is less than sh_invalid_cnt_max and block_lock is asserted, goback to the TEST_SH state. The main thing to note with this state machine is that toachieve block lock, one must receive sh_cnt_max number of valid sync headers in arow without getting an invalid sync header. However, once block lock is achieved,sh_invalid_cnt_max -1 number of invalid sync headers can be received withinsh_cnt_max number of valid sync headers. Thus, once locked, it is harder to break lock.Functions Common to All ProtocolsClock CorrectionClock correction is needed when the rate that data is fed into the write side of the receiveFIFO is either slower or faster than the rate that data is retrieved from the read side of thereceive FIFO. The rate of write data entering the FIFO is determined by the frequency ofRXRECCLK. The rate of read data retrieved from the read side of the FIFO is determinedby the frequency of RXUSRCLK.There is one clock correction mode: Append/Remove Idle Clock Correction.Append/Remove Idle Clock CorrectionWhen the attribute CLK_COR_SEQ_DROP is asserted Low and CLK_CORRECT_USE isasserted hIgh, the Append/remove Idle Clock Correction mode is enabled.The Append/remove Idle Clock Correction mode corrects for differing clock rates byfinding idles in the bitstream, and then either appending or removing idles at the pointwhere the idles were found.There are a few attributes that need to be set by the user so that the append/removefunction can be used correctly. The attribute CLK_COR_MAX_LAT sets the maximumlatency through the receive FIFO. If the latency through the receive FIFO exceeds thisvalue, idles are removed so that latency through the receive FIFO is less thanCLK_COR_MAX_LAT.The attribute CLK_COR_MIN_LAT sets the minimum latency through the receive FIFO. Ifthe latency through the receive FIFO is less than this value, idles are inserted so that thelatency through the receive FIFO are greater than CLK_COR_MIN_LAT. A correction tothe latency due to a CLK_COR_MAX_LAT violation is never less than