Xilinx RocketIO X User Manual

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Xilinx RocketIO X User Manual Manual pdf 48 page image

48 www.xilinx.com RocketIO™ X Transceiver User Guide1-800-255-7778 UG035 (v1.5) November 22, 2004Chapter 2: Digital Design ConsiderationsREncoderA bypassable 8B/10B encoder is included in the transmitter. The encoder uses the same256 data characters and 12 control characters (shown in Appendix B, “8B/10B ValidCharacters”) that are used for Gigabit Ethernet, XAUI, Fibre Channel, and InfiniBand.The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits percharacter applied. If the K-character signal is High, the data is encoded into one of the 12possible K-characters available in the 8B/10B code. If the K-character input is Low, the8 bits are encoded as standard data.There are two ports that enable the 8B/10B encoding in the transceiver. TheTXBYPASS8B10B is a byte-mapped port that is 1, 2, 4 or 8 bits depending on the data widthof the transceiver primitive being used. These bits correlate to each byte of the data path.To enable the 8B/10B encoding of the transmitter, these bits should be set to a logic 0. Inthis mode, the transmit data that is input to the TXDATA port is non-encoded data of either8, 16, 32, or 64 bits wide. However, if other encoding schemes are preferred, the encodercapabilities are bypassed by setting all bits to a logic 1. The extra bits are fed through theTXCHARDISPMODE and TXCHARDISPVAL buses.TXCHARDISPVAL and TXCHARDISPMODETXCHARDISPVAL and TXCHARDISPMODE are dual-purpose ports for the transmitterdepending whether 8B/10B encoding is done. Table 2-6 shows this dual functionality.When encoding is enabled, these ports function as byte-mapped control ports controllingthe running disparity of the transmitted serial data (Table 2-5).In the encoding configuration, the disparity of the serial transmission can be controlledwith the TXCHARDISPVAL and TXCHARDISPMODE ports. When TXCHARDISPMODEis set to a logic 1, the running disparity is set before encoding the specific byte.TXCHARDISPVAL determines if the disparity is negative (set to a logic 0) or positive (setto a logic 1).When TXCHARDSIPMODE is set to a logic 0, the running disparity is maintained ifTXCHARDISPVAL is also set to a logic 0. However, the disparity is inverted beforeencoding the byte when the TXCHARDISPVAL is set to a logic 1.Most applications use the mode where both TXCHARDISPMODE and TXCHARDISPVALare set to logic 0. Some applications can use other settings if special running disparityconfigurations are required, such as in the “Vitesse Disparity Example,” page 52.In the bypassed configuration, TXCHARDISPMODE[0] becomes bit 9 of the 10 bits ofencoded data (TXCHARDISPMODE[1:7] are bits 19, 29, 39, 49, 59, 69, and 79 in the 20-bitand 40-bit and 80-bit wide buses). TXCHARDISPVAL becomes bits 8, 18, 28, 38, 48, 58, 68,and 78 of the transmit data bus while the TXDATA bus completes the bus. See Table 2-6.Table 2-5: Running Disparity Control{txchardispmode,txchardispval} Function00 Maintain running disparity normally01 Invert normally generated running disparity beforeencoding this byte10 Set negative running disparity before encoding this byte11 Set positive running disparity before encoding this byte