42 www.xilinx.com RocketIO™ X Transceiver User Guide1-800-255-7778 UG035 (v1.5) November 22, 2004Chapter 2: Digital Design ConsiderationsRTop-Level ArchitectureTransmit ArchitectureThe transmit architecture for the PCS is shown in Figure 2-1. For information aboutbypassing particular blocks, consult the block function section for that particular block.Receive ArchitectureThe receive architecture for the PCS is shown in Figure 2-2. For information aboutbypassing particular blocks, consult the block function section for that particular block.Figure 2-1: Transmit Architecture6x40 bitTXFIFO 8B/10BEncodeGearbox10G EncodeTXUSRCLKTXUSRCLK2TXENC8B10BUSETXENC6466USETXSCRAM64B66BUSETXGEARBOX64B66BUSETXPOLARITYPMAScramblerPMAConvertTX_BUFFER_USEResetControlPMAAttributeLoadFabric ConvertPMAINITUG035_CH3_01_092903TXDATATXRESETTXPTXNFigure 2-2: Receive ArchitectureRXCLK0PMA/PCS BoundaryRX ElasticBuffer16x52Channel Bonding & ClockCorrectionFabric8B/10BDecodeComma DetectAlign10GBlockSync10GDecode10GDescrRXRECCLK RXUSRCLKRXUSRCLK2Sync State MachineRXBLOCKSYNCUSE,RXVALUEDETUSERXDEC8B10BUSE,RXDESCRAM64B66BUSE RX_BUFFER_USERXDEC6466USESLIPReset ControlHOLDOFFUG035_CH3_02_092903ENPCOMMAALIGNENMCOMMAALIGNRXPOLARITYLOCKCHBONDRX Data Word Alignment MuxRXDATARXRESET
