RocketIO™ X Transceiver User Guide www.xilinx.com 151UG035 (v1.5) November 22, 2004 1-800-255-7778Register Definition RTXBUSWIDTXBUSWID selects between wide and narrow internal parallel transmit data bus. Thedefault is 1 (Wide). The bus width settings are defined as follows:TXLOOPFILTERC[1:0]TXLOOPFILTERC[1:0] selects the transmit PLL filter capacitor setting. The default isprimitive dependent. The loop filter capacitor selection is as follows:TXLOOPFILTERR[1:0]TXLOOPFILTERR[1:0] selects the transmit PLL filter resistor setting. The default isprimitive dependent. The loop filter resistor selection is as follows:1010 ÷ 201011 Reserved1100 Reserved1101 Reserved1110 Reserved1111 ReservedTable C-6: TXOUTCLK Divider Ratio Definition (Continued)TXDIVRATIO[9:6] DividerTable C-7: TXBUSWID DefinitionTXBUSWID TX Parallel Bus Width0 16/20 bit1 32/40 bit (default)Table C-8: TXLOOPFILTERC[1:0] DefinitionTXLOOPFILTERC[1:0] TX Filter Capacitor00 15 pF01 30 pF10 45 pF11 60 pFTable C-9: TXLOOPFILTERR[1:0] DefinitionTXLOOPFILTERR[1:0] TX Filter Resistor00 12 kΩ01 6 kΩ
