RocketIO™ X Transceiver User Guide www.xilinx.com 73UG035 (v1.5) November 22, 2004 1-800-255-7778RChapter 3Clocking and Clock DomainsClock Domain ArchitectureThere are seven clock inputs into each RocketIO X transceiver instantiation. REFCLK,REFCLK2, and BREFCLK are clocks generated from an external source. BREFCLK is a setof differential inputs into the FPGA that can create a clock tree for all MGTs on one side ofthe device. See Figure 3-1. The reference clocks connect to the REFCLK, REFCLK2, orBREFCLK of the RocketIO X Multi-Gigabit Transceiver (MGT). While only one of thesereference clocks is needed to drive the MGT, BREFCLK inputs for the reference clock arerecommended for the best operation. All characterization and data sheet numbers use theBREFCLK. Therefore, REFCLK usage results in performance degradation from thepublished performance numbers. BREFCLK also clocks a Digital Clock Manager (DCM) togenerate all of the other clocks for the MGT.Note: Do not run a reference clock through a DCM; jitter control is optimized on reference clock netswithout the use of a DCM.Note: BREFCLK inputs can only be used to drive the MGTs and DCMs.xFigure 3-1: Reference Clock Selection01 1REFCLKBSELREFCLKSELREFCLKREFCLK2BREFCLKPINBREFCLKNIN0 LocalPMA/PCSReferenceFromFPGAFabricug035_ch3_11_030404
