Xilinx Spartan-6 FPGA User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideUser guideDesign and pin planning guideUser guide
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Spartan-6 FPGA Power Management www.xilinx.com 17UG394 (v1.1) September 4, 2012Suspend Mode Wake-Up Timing ControlsDesign Requirements to Maintain Application DataWhen a design requires that application data be preserved when entering suspend mode,the SUSPEND_SYNC primitive should be used. When the FPGA enters suspend mode, theglobal write enable (GWE) is removed, maintaining the state of all flip-flops and userRAM. The FPGA requires a delay of tSUSPEND_GWE between recognizing a High on theSUSPEND pin and disabling GWE internally. This is the first event after SUSPENDtransitions High, before AWAKE toggles, and before the inputs are disabled ifSUSPEND_SYNC is not used. During this delay, additional user clocks to flip-flops orRAM can continue to update their contents. Since the GWE signal can have some skewbetween locations on the device, some locations can be disabled while others remainenabled on the last clock edge before GWE takes full effect. This situation can be avoidedwhen using the SUSPEND_SYNC feature. After the suspend request is driven out of theSUSPEND_SYNC primitive, disable the clocks and/or clock enables on the logic that mustretain its current state. After the disable is complete, drive the SACK port of theSUSPEND_SYNC primitive and the FPGA begins the process to enter suspend mode.To avoid initializing the flip-flops when exiting suspend mode, choose en_sw_gsr:No.Exiting suspend mode should be synchronized to a user clock to avoid race conditionscorrupting the application data. Inputs are enabled first, allowing control signals tocontinue to hold off the toggling of storage primitives. The assertion of GWE can besynchronized to a user clock to align it with a system clock edge.Suspend Mode Wake-Up Timing ControlsWhen exiting suspend mode, the wake-up sequence for the FPGA is programmable andcontrolled by a single clock.Wake-Up Timing Clock SourceThe wake-up timing when exiting suspend mode is controlled by a selectable clock sourceas shown in Figure 1-4 and described in Table 1-3. The clock source is defined by one ortwo bitstream generator options, sw_clk and sometimes StartupClk.The internal oscillator is disabled during suspend mode to conserve power. |
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