Xilinx Spartan-6 FPGA User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideUser guideDesign and pin planning guideUser guide
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Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012Notice of DisclaimerThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximumextent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALLWARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whetherin contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arisingunder, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, orconsequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any actionbrought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products aresubject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may besubject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to befail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in CriticalApplications: http://www.xilinx.com/warranty.htm#critapps.© Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, Vivado, and other designated brandsincluded herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respectiveowners.Revision HistoryThe following table shows the revision history for this document.Date Version Revision05/18/10 1.0 Initial Xilinx release.09/04/12 1.1 • Updated Additional Documentation section.• In Chapter 1, deleted first and last paragraphs from Differential I/O Standards.Eliminated statements pertaining to differential drivers and receivers disabled insuspend mode. Reinforced the directive that the SUSPEND pin must be tied to GNDwhen the suspend feature is disabled by adding “or High” to second paragraph ofSUSPEND Pin. Changed “X” to “0” in first row of Table 1-5. Changed the AWAKEoutput pin power supply to V CCO power rail on bank 1 in third paragraph of AWAKEPin Behavior when Suspend Feature is Enabled. Added “for RecommendedOperating Conditions” to data sheet power levels referenced in FPGA VoltageRequirements During Suspend Mode.• In Chapter 2, changed “used” to “being programmed” in description section, last row,of Table 2-1. Added VCCAUX setting restriction paragraphs to VCCAUX. Removed“± 5%” specification from first paragraph in VCCAUX Specifications and thirdparagraph of VCCO.• In Chapter 3, removed “approximately one speed grade slower (~15%)” from firstparagraph in Introduction. Added a UG382 reference to Designing Using theLower-Power Spartan-6 LX Devices. Added VCCAUX and IODELAY2 specificationparagraphs to Lower-Power Spartan-6 LX Device Specifications.• In Chapter 5, removed “50%” specification from second paragraph in Saving Power.Also remove last sentence referencing techniques for past FPGA families from lastparagraph in ISE Design Suite Power Optimization. |
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