Xilinx Spartan-6 FPGA User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideUser guideDesign and pin planning guideUser guide
                                        | |
Contents
| 
Spartan-6 FPGA Power Management www.xilinx.com 39UG394 (v1.1) September 4, 2012ISE Design Suite Power OptimizationSaving Clock Routing PowerClocks are a significant aspect of power consumption because of their high fanout nets andalso because controlling them limits the number of logic primitives toggling in a design. Ifpossible, stop the clock where it enters the FPGA, so that it does not consume any FPGApower. If the clock can not be gated externally, then disable it inside the FPGA using theBUFGCE primitive. Avoid using logic to gate clocks, since CLB logic introducesroute-dependent skew and makes the design sensitive to the timing hazards of lot-to-lotvariations. Minimizing the amount of routing a clock net uses is helpful, since the Xilinxsoftware automatically disables clock nets where possible for unused areas of CLBs.If possible, minimize the number of DCMs or PLLs required in the design. A single PLLcan be shared with both halves of a GTP_DUAL transceiver. A DCM_CLKGEN can beused to dynamically scale clock frequency as needed for the application, helping tominimize power.ISE Design Suite Power OptimizationPower can also be reduced automatically in the Xilinx design tools. With goal-basedimplementation, the ISE Design Suite offers a simple, one-step process to specify poweroptimization. Design Goals and Strategies control the implementation tools by usingpreset process properties designed to achieve a particular design goal. Power optimizationattempts to meet timing constraints as well as reduce power consumption.For guidelines on design techniques to reduce power consumption, see the PowerAdvantage page at:http://www.xilinx.com/products/technology/power/index.htm |
Related manuals for Xilinx Spartan-6 FPGA Series
This manual is suitable for:
manualsdatabase
Your AI-powered manual search engine