Xilinx Spartan-6 FPGA User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideUser guideDesign and pin planning guideUser guide
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Contents
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36 www.xilinx.com Spartan-6 FPGA Power ManagementUG394 (v1.1) September 4, 2012Chapter 4: Power-On and Power-Down Behavior Including HibernateExiting HibernateThe steps for exiting Hibernate are as follows.1. Reapply power to all rails that were switched off. Apply power in any sequence.2. Before FPGA initialization can begin, deassert PROGRAM_B to a High logic level. Therising transition on PROGRAM_B must occur after turning all three power suppliesback on.3. After logic initialization, the FPGA releases the open-drain INIT_B signal. WithINIT_B High, the FPGA starts its configuration process.4. When configuration is complete, the FPGA enters the Start-up phase, asserts DONE,and enables the I/Os, according to how the BitGen options are set.5. The FPGA is now ready for user operation.Design ConsiderationsBe aware of how various pins are powered in the application. Most user-I/O pins,including the dual-purpose configuration pins and the dedicated PROGRAM_B andDONE pins, are powered by a specific V CCO supply input. Dedicated configuration pinssuch as SUSPEND and the JTAG pins are powered by the V CCAUX supply. If disconnectingpower to any of these supplies, consider how that affects FPGA configuration when poweris re-applied.For specific information on configuration pins and their associated power rails, refer toUG380, Spartan-6 FPGA Configuration User Guide. |
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