Xilinx Spartan-6 FPGA User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideUser guideDesign and pin planning guideUser guide
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34 www.xilinx.com Spartan-6 FPGA Power ManagementUG394 (v1.1) September 4, 2012Chapter 4: Power-On and Power-Down Behavior Including HibernateForcing FPGA to Quiescent Current LevelsBefore removing the power supplies, it is recommended to first put the device into thequiescent state. Pulse PROGRAM_B Low to achieve the quiescent current levels. DrivingPROGRAM_B Low forces all I/Os into a high-impedance state, ceases all internalswitching, and converts the bitstream held in internal memory to all zeros. During andafter the Low pulse on PROGRAM_B, disable the internal pull-up resistors on all I/Os bydriving the HSWAPEN input High. Holding PROGRAM_B Low continues clearing theconfiguration memory. To minimize quiescent current, release PROGRAM_B High buthold off configuration by holding INIT_B Low, or by setting the Mode pins to a slave orJTAG configuration mode and disabling the external configuration clock (CCLK or TCK).To restart the application, release PROGRAM_B High and in slave or JTAG modes, enablethe external configuration source. The FPGA must reconfigure before the applicationrestarts. No state information is preserved. If the application must retain the FPGAconfiguration bitstream, then use the suspend mode.Entering Hibernate StateHibernate starts with the approach described in Forcing FPGA to Quiescent CurrentLevels, page 34. Hibernate provides further power savings by switching off power rails.This state reduces quiescent power consumption to the lowest possible level. The FPGAenters Hibernate by switching off the VCCINT (core), V CCAUX (auxiliary), and VCCO(output) power supplies. Power FETs with low on resistance are recommended to performthe switching action. Configuration data is lost upon entering Hibernate; therefore, thedevice reconfigures after exiting the state.Holding the PROGRAM_B input Low during the transition into Hibernate keeps all FPGAoutput drivers in a high-impedance state. Release PROGRAM_B after re-applying power.See Design Considerations, page 36 for recommended levels on Dedicated andDual-Purpose pins.X-Ref Target - Figure 4-2Figure 4-2: Spartan-6 FPGA Power-Off DiagramVCCAUXPROGRAM_BActive DeviceConnected onBoardUG394_c4_02_111109PowerSwitch2.5V/3.3V 1.2V/1.0VVCCINT VCCOV CCOSupplySpartan-6FPGA |
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