Xilinx Spartan-6 FPGA User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideUser guideDesign and pin planning guideUser guide
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Spartan-6 FPGA Power Management www.xilinx.com 19UG394 (v1.1) September 4, 2012Dedicated Configuration Pins Unaffected During Suspend ModeSwitch Outputs from Suspend to Normal BehaviorThe suspend/wake sw_gts_cycle bitstream option controls when I/O pins are releasedfrom their SUSPEND attribute settings and returned to normal operation. The timing iscontrolled by the Wake-Up Timing Clock Source, page 17. The default sw_gts_cycle settingis four cycles, but this control can be set for any value between one and 1,024 clock cycles.The suspend/wake control becomes active after the AWAKE pin transitions High. Afterthe specified number of clock cycles, all output, open-drain output, and bidirectional I/Opins transition from their suspend behavior, either the default 3STATE or individuallyspecified using the SUSPEND attribute, back to the normal behavior specified in theoriginal FPGA application.The outputs should be released before releasing the write-protect lock on all clockedprimitives.Release Write Protect on Clocked PrimitivesThe suspend/wake sw_gwe_cycle bitstream option controls when the write-protect lock isreleased on all clocked primitives.The timing is controlled by sw_clk the Wake-Up Timing Clock Source, page 17. The defaultsw_gwe_cycle setting is five cycles, but the suspend/wake control can be set for any valuebetween one and 1,024 clock cycles.This suspend/wake control becomes active after the AWAKE pin transitions High. Afterthe specified number of clock cycles, the write-protect lock is released from all writable,clocked primitives such as flip-flops, block RAM, etc.When the en_sw_gsr:yes option is set, the clocked primitives are already globally set orreset to the value specified in the original FPGA design before the write-protect lock isreleased. The option en_sw_gsr:no signifies that the state of the FPGA after enteringsuspend mode is preserved.The outputs should be released before releasing the write-protect lock on all clockedprimitives.Dedicated Configuration Pins Unaffected During Suspend ModeThe following dedicated configuration pins are unaffected when the FPGA is in suspendmode:• JTAG pins: TDI, TMS, TCK, and TDO• DONE pin• PROGRAM_B pinJTAG Operations Allowed During Suspend ModeTable 1-4 shows the JTAG operations permitted when the FPGA is in suspend mode.Executing these JTAG operations increases the FPGA's power consumption while insuspend mode. |
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