Xilinx Virtex-5 FPGA ML550 User Manual

Also see for Virtex-5 FPGA ML561: User guide User guide User guide User guide User guide

Contents

ML550 Networking Interfaces Platform www.xilinx.com 29UG202 (v1.4) April 18, 2008Voltage Regulators (TI PTH05000)Routputs a halved frequency on pins U17.12 and U17.11, DIVCLK_P and DIVCLK_Nrespectively. As previously mentioned, these output pins are connected to the FPGA.LVDS Loopback Board (Xilinx P/N 0431395)LVDS transmit to receive loopback can be achieved with either the LVDS Loopback boardincluded in the kit, or with the Precision Interconnect Blue Ribbon Cables (Xilinx P/NHW-LVDS-CBL-80, order separately). Appendix B, “LVDS Loopback Board” includesLVDS Loopback Board details.Voltage Regulators (TI PTH05000)Figure 3-7 shows the voltage regulators used on ML550 Development Board to providevarious on-board voltage sources. As shown in Figure 3-7, connector J20 provides the main5.0V voltage to the board. This voltage source is provided to all on-board regulators togenerate the 1.0V, 2.5V, and 3.3V voltages for the digital section of the board. All BankV CCO voltages are 2.5V.Onboard digital voltages are as follows:• 1.0V VCCINT (VR2)• 2.5V VCCAUX (VR5)• 2.5V VCCO (VR4)• 2.5V System (VR3)• 3.3V System (VR1)Voltage Regulator ±5% Margin Adjustment (in 2.5% Increments)The regulators shown in Table 3-9 can have their outputs controlled over a ±5% range bythe FPGA, or they can be enabled or inhibited through the use of on-board jumpers. Thejumpers use the following conventions:Figure 3-7: Block Diagram of the Five Voltage Regulators3.3VRegulatorVR1 VR3 VR4 VR5 VR2System3.3V2.5VRegulatorSystem2.5V2.5VRegulatorV CCO2.5V2.5VRegulatorV CCAUX2.5V1.0VRegulatorV CCINT1.0VJ20On/OffSW83 AmpFuse5VF12.1 mmBarrelPlugUG202_3_07_120706AC to DCConverter5V DC @6A+−